Design of Low-Power Area-Efficient Shift Register Using Transmission Gate

The shift register is sequential logic circuit to store the digital data, also basic structure block in VLSI circuit. This proposes a low-power and area-efficient shift register using transmission gate. Shift register is used small number of pulse clock signal by alignment latches to several shift register and additional temporary latches. The non-stop flow of pulse signal from input side due to this unnecessary of signal flow so the power and delay will essential more, as to overcome this Clock Gating technique is used. The area and power consumption are compact by replacing latches with transmission gate. The area, power, and transistor count have been compared and designed using several latches and flip-flop stages. This technique solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. Clock Gating technique is used for power consumption also delay factor as much as low and latches should be replaced by transmission gate. The static sense amp shared pulse latch (SSASPL) which is the smallest latch has been selected and also power PC Style flip-flop (PPCFF) which is used for calculating power, area, and delay. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub-shift registers and using additional temporary storage latches. The analysis is carried out using Tanner EDA–Industry Standard EDA design environment using 180 nm technologies. The simulation results are shown. A four-bit shift register using transmission gate in tanner tools used V_DD = 3.3 V and power consumption is 1.063 μW.