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Erschienen in: Journal of Electronic Testing 4/2021

25.08.2021

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

verfasst von: Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen

Erschienen in: Journal of Electronic Testing | Ausgabe 4/2021

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Abstract

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

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Literatur
1.
Zurück zum Zitat Calin T, Nicolaidis M, Velazco R (1996) Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans Nucl Sci 43(6):2874–2878CrossRef Calin T, Nicolaidis M, Velazco R (1996) Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans Nucl Sci 43(6):2874–2878CrossRef
2.
Zurück zum Zitat Eftaxiopoulos N, Axelos N, Pekmestzi K (2015) DONUT: A Double Node Upset Tolerant Latch. Proc. IEEE Annual Symposium on VLSI, Montpellier, France, pp 509–514 Eftaxiopoulos N, Axelos N, Pekmestzi K (2015) DONUT: A Double Node Upset Tolerant Latch. Proc. IEEE Annual Symposium on VLSI, Montpellier, France, pp 509–514
3.
Zurück zum Zitat Eftaxiopoulos N, Axelos N, Zervakis G, Tsoumanis K, Pekmestzi K (2015) Delta DICE: A Double Node Upset Resilient Latch. Proc. IEEE International Midwest Symposium on Circuits and Systems, Fort Collins, USA, pp 1–4 Eftaxiopoulos N, Axelos N, Zervakis G, Tsoumanis K, Pekmestzi K (2015) Delta DICE: A Double Node Upset Resilient Latch. Proc. IEEE International Midwest Symposium on Circuits and Systems, Fort Collins, USA, pp 1–4
4.
Zurück zum Zitat Fazeli M, Miremadi S, Ejlali A, Patooghy A (2009) Low Energy Single Event Upset/Single Event Transient-Tolerant Latch for Deep Submicron Technologies. IET Comput Digital Tech 3(3):289–303CrossRef Fazeli M, Miremadi S, Ejlali A, Patooghy A (2009) Low Energy Single Event Upset/Single Event Transient-Tolerant Latch for Deep Submicron Technologies. IET Comput Digital Tech 3(3):289–303CrossRef
5.
Zurück zum Zitat Huang Z (2014) A High Performance SEU Tolerant Latch for Nanoscale CMOS Technology. Proc. IEEE Design Automation Test in Europe, Dresden, Germany, pp 1–5 Huang Z (2014) A High Performance SEU Tolerant Latch for Nanoscale CMOS Technology. Proc. IEEE Design Automation Test in Europe, Dresden, Germany, pp 1–5
6.
Zurück zum Zitat Huang Z, Liang H, Hellebrand S (2015) A High Performance SEU Tolerant Latch. Journal of Electronics Testing 31:349–359CrossRef Huang Z, Liang H, Hellebrand S (2015) A High Performance SEU Tolerant Latch. Journal of Electronics Testing 31:349–359CrossRef
7.
Zurück zum Zitat Huang Z, Liang H, Hellebrand S (2015) A High Performance SNU Tolerant Latch. J Electron Test 31(4):349–359CrossRef Huang Z, Liang H, Hellebrand S (2015) A High Performance SNU Tolerant Latch. J Electron Test 31(4):349–359CrossRef
8.
Zurück zum Zitat Hui X, Yun Z (2015) Circuit and Layout Combination Technique to Enhance Multiple Nodes Upset Tolerance in Latches. IEICE Electronics Express 12(9):1–7CrossRef Hui X, Yun Z (2015) Circuit and Layout Combination Technique to Enhance Multiple Nodes Upset Tolerance in Latches. IEICE Electronics Express 12(9):1–7CrossRef
9.
Zurück zum Zitat Jiang J, Xu Y, Ren J, Zhu W, Lin D, Xiao J, Kong W, Zou S (2018) Low-Cost Single Event Double-Upset Tolerant Latch Design. Electron Lett 54(9):554–556CrossRef Jiang J, Xu Y, Ren J, Zhu W, Lin D, Xiao J, Kong W, Zou S (2018) Low-Cost Single Event Double-Upset Tolerant Latch Design. Electron Lett 54(9):554–556CrossRef
10.
Zurück zum Zitat Katsarou K, Tsiatouhas Y (2014) Double Node Charge Sharing SEU Tolerant Latch Design,” Proc. IEEE International Symposium on On-Line Testing and Robust System Design, Platja d'Aro, Spain, pp. 122–127 Katsarou K, Tsiatouhas Y (2014) Double Node Charge Sharing SEU Tolerant Latch Design,” Proc. IEEE International Symposium on On-Line Testing and Robust System Design, Platja d'Aro, Spain, pp. 122–127
11.
Zurück zum Zitat Katsarou K, Tsiatouhas Y (2015) Soft Error Interception Latch: Double Node Charge Sharing SNU Tolerant Design. Electron Lett 51(4):330–332CrossRef Katsarou K, Tsiatouhas Y (2015) Soft Error Interception Latch: Double Node Charge Sharing SNU Tolerant Design. Electron Lett 51(4):330–332CrossRef
12.
Zurück zum Zitat Li Y, Wang H, Liu R, Chen L, Nofal I, Shi S, He A, Guo G, Baeg S, Wen S, Wong R, Chen M, Wu Q (2017) A Quatro-Based 65 nm Flip-Flop Circuit for Soft-Error Resilience. IEEE Trans Nucl Sci 64(6):1554–1561 Li Y, Wang H, Liu R, Chen L, Nofal I, Shi S, He A, Guo G, Baeg S, Wen S, Wong R, Chen M, Wu Q (2017) A Quatro-Based 65 nm Flip-Flop Circuit for Soft-Error Resilience. IEEE Trans Nucl Sci 64(6):1554–1561
13.
Zurück zum Zitat Li Y, Wang H, Liu R, Chen L, Nofal I, Chen Q, He A, Guo G, Baeg S, Wen S, Wong R, Wu Q, Chen M (2016) A 65 nm Temporally Hardened Flip-Flop Circuit. IEEE Trans Nucl Sci 63(6):2934–2940CrossRef Li Y, Wang H, Liu R, Chen L, Nofal I, Chen Q, He A, Guo G, Baeg S, Wen S, Wong R, Wu Q, Chen M (2016) A 65 nm Temporally Hardened Flip-Flop Circuit. IEEE Trans Nucl Sci 63(6):2934–2940CrossRef
14.
Zurück zum Zitat Li Y, Wang H, Yao S, Yan X, Gao Z, Xu J (2015) Double Node Upsets Hardened Latch Circuits. Journal of Electronics Testing 31:537–548CrossRef Li Y, Wang H, Yao S, Yan X, Gao Z, Xu J (2015) Double Node Upsets Hardened Latch Circuits. Journal of Electronics Testing 31:537–548CrossRef
15.
Zurück zum Zitat Li H, Xiao L, Qi C (2019) High Robust and Cost Effective Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 93:89–97CrossRef Li H, Xiao L, Qi C (2019) High Robust and Cost Effective Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 93:89–97CrossRef
16.
Zurück zum Zitat Lin S, Kim Y, Lombardi F (2011) Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. IEEE Transactions on Very Large Scale Integration VLSI Systems 19(7):1315–1319CrossRef Lin S, Kim Y, Lombardi F (2011) Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. IEEE Transactions on Very Large Scale Integration VLSI Systems 19(7):1315–1319CrossRef
17.
Zurück zum Zitat Lin D, Xu Y, Li X, Xie X, Jiang J, Ren J, Zhu H, Zhang Z, Zou S (2018) A Novel Self-Recoverable and Triple Nodes Upset Resilience DICE Latch. IEICE Electronics Express 15(19):1–10CrossRef Lin D, Xu Y, Li X, Xie X, Jiang J, Ren J, Zhu H, Zhang Z, Zou S (2018) A Novel Self-Recoverable and Triple Nodes Upset Resilience DICE Latch. IEICE Electronics Express 15(19):1–10CrossRef
18.
Zurück zum Zitat Mavis D, Eaton P (2007) SEU and SET Modeling and Mitigation in Deep Submicron Technologies. Proc. IEEE International Reliability Physics Symposium, Phoenix, USA, pp 293–305 Mavis D, Eaton P (2007) SEU and SET Modeling and Mitigation in Deep Submicron Technologies. Proc. IEEE International Reliability Physics Symposium, Phoenix, USA, pp 293–305
19.
Zurück zum Zitat Mitra S, Zhang M, Seifert N, Mak T, Kim K (2007) Built-in Soft Error Resilience for Robust System Design. Proc IEEE International Conference on IC Design and Technology, Austin, USA, pp. 1–6 Mitra S, Zhang M, Seifert N, Mak T, Kim K (2007) Built-in Soft Error Resilience for Robust System Design. Proc IEEE International Conference on IC Design and Technology, Austin, USA, pp. 1–6
20.
Zurück zum Zitat Namba K, Sakata M, Ito H (2010) Single Event Induced Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Kyoto, Japan, pp. 280–288 Namba K, Sakata M, Ito H (2010) Single Event Induced Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Kyoto, Japan, pp. 280–288
21.
Zurück zum Zitat Nan H, Choi K (2012) High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans Circuits Syst I Regul Pap 59(7):445–1457MathSciNetCrossRef Nan H, Choi K (2012) High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans Circuits Syst I Regul Pap 59(7):445–1457MathSciNetCrossRef
22.
Zurück zum Zitat Nan H, Choi K (2012) Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 52:1209–1214CrossRef Nan H, Choi K (2012) Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 52:1209–1214CrossRef
23.
24.
Zurück zum Zitat Peng C, Xiao S, Lu W, Zhang J, Wu X, Chen J, Lin Z (2018) Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans Very Large Scale Integr VLSI Syst 26(3):584–588CrossRef Peng C, Xiao S, Lu W, Zhang J, Wu X, Chen J, Lin Z (2018) Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans Very Large Scale Integr VLSI Syst 26(3):584–588CrossRef
25.
Zurück zum Zitat Qi C, Xiao L, Guo J (2015) Low Cost and Highly Reliable Radiation Hardened Latch Design in 65 nm CMOS Technology. Microelectron Reliab 55:863–872CrossRef Qi C, Xiao L, Guo J (2015) Low Cost and Highly Reliable Radiation Hardened Latch Design in 65 nm CMOS Technology. Microelectron Reliab 55:863–872CrossRef
26.
Zurück zum Zitat Ramin R (2017) Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits. Microelectron Reliab 69:109–114CrossRef Ramin R (2017) Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits. Microelectron Reliab 69:109–114CrossRef
27.
Zurück zum Zitat She X, Li N, Tong J (2012) SEU Tolerant Latch Based on Error Detection. IEEE Trans Nucl Sci 59(1):211–214CrossRef She X, Li N, Tong J (2012) SEU Tolerant Latch Based on Error Detection. IEEE Trans Nucl Sci 59(1):211–214CrossRef
28.
Zurück zum Zitat Watkins A, Tragouodas S (2016) A Highly Robust Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Storrs, USA, pp. 15–20 Watkins A, Tragouodas S (2016) A Highly Robust Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Storrs, USA, pp. 15–20
29.
Zurück zum Zitat Watkins A, Tragouodas S (2017) Radiation Hardened Latch Designs for Double and Triple Node Upsets. IEEE Trans Emerg Top Comput 99:1–10 Watkins A, Tragouodas S (2017) Radiation Hardened Latch Designs for Double and Triple Node Upsets. IEEE Trans Emerg Top Comput 99:1–10
30.
Zurück zum Zitat Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) “Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans Very Large Scale Integr VLSI Syst 25(6):1978–1982CrossRef Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) “Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans Very Large Scale Integr VLSI Syst 25(6):1978–1982CrossRef
31.
Zurück zum Zitat Yan A, Lai L, Zhang Y, Cui J, Huang Z, Song J, Guo J, Wen X (2018) Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. IEEE Trans Emerg Top Comput 99:1–14 Yan A, Lai L, Zhang Y, Cui J, Huang Z, Song J, Guo J, Wen X (2018) Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. IEEE Trans Emerg Top Comput 99:1–14
32.
Zurück zum Zitat Yan A, Liang H, Huang Z, Jiang C, Yi M (2015) A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. IEICE Trans Electron 98(12):1171–1178CrossRef Yan A, Liang H, Huang Z, Jiang C, Yi M (2015) A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. IEICE Trans Electron 98(12):1171–1178CrossRef
33.
Zurück zum Zitat Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. Proc IEEE Asian Test Symposium, pp. 43–48, Kolkata, India Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. Proc IEEE Asian Test Symposium, pp. 43–48, Kolkata, India
34.
Zurück zum Zitat Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Radiation-Hardened 14T SRAM Bitcell with Speed and Power Optimized for Space Application. IEEE Trans Very Large Scale Integr VLSI Syst 27(2):407–415CrossRef Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Radiation-Hardened 14T SRAM Bitcell with Speed and Power Optimized for Space Application. IEEE Trans Very Large Scale Integr VLSI Syst 27(2):407–415CrossRef
35.
Zurück zum Zitat Yan A, Yang K, Huang Z, Zhang J, Cui J, Fang X, Yi M, Wen X (2019) A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans Circuits Syst II Express Briefs 66(2):287–291CrossRef Yan A, Yang K, Huang Z, Zhang J, Cui J, Fang X, Yi M, Wen X (2019) A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans Circuits Syst II Express Briefs 66(2):287–291CrossRef
36.
Zurück zum Zitat Zhang H, Liu Z, Jiang J, Xiao J, Zhang Z, Zou S (2020) High-Performance and Single Event Double-Upset-Immune Latch Design. Electron Lett 56(23):1243–1245CrossRef Zhang H, Liu Z, Jiang J, Xiao J, Zhang Z, Zou S (2020) High-Performance and Single Event Double-Upset-Immune Latch Design. Electron Lett 56(23):1243–1245CrossRef
Metadaten
Titel
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications
verfasst von
Aibin Yan
Aoran Cao
Zhelong Xu
Jie Cui
Tianming Ni
Patrick Girard
Xiaoqing Wen
Publikationsdatum
25.08.2021
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 4/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-021-05962-0

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