17. Design of SRAM Resilient Against Dynamic Voltage Variations

This chapter deals with the design of SRAM cache resilient against dynamic voltage and temperature variations. The scaled CMOS SRAM suffers from a voltage margin reduction owing to the rising of the minimum operating voltage (Vmin), resulting in lower immunity against the dynamic voltage bounce on the power line. In order to solve this critical issue, the authors have proposed a resilient cache which is composed of a 256-KB 8-way cache memory array with 7T/14T bit-enhancing (BE) SRAM, voltage and temperature monitoring circuits, and an autonomous resilient cache controller. The autonomous controller detects degradation of the operating margin caused by the voltage and temperature fluctuation. If the margin is insufficient for stable operation, the controller changes the operating mode of 7T/14T bit-enhancing SRAM from 7T/bit normal operating mode to more reliable 14T/bit-enhancing mode. This adaptive control enables maintenance of the required voltage margin in the current operating condition. The experimental cache was designed and fabricated by 40 nm CMOS technology. The voltage variation tolerance of the resilient cache was evaluated using a voltage droop injection to the external power supply rail. Under 25 and 30% droop conditions, the failures increase linearly with droop duration length without the proposed scheme. Using the proposed scheme, the resilient cache does not fail irrespective of the droop duration length. The failure rate is improved by 91 times of that without the proposed scheme under 35% droop condition with 50 ms duration. The capacity decrease degrades processor performance only by 2.88% when all blocks operate in the enhancing mode.