Skip to main content

2014 | OriginalPaper | Buchkapitel

3. DfM at 28 nm and Beyond

verfasst von : Artur Balasinski

Erschienen in: Design for Manufacturability

Verlag: Springer New York

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Introduction of more advanced technology nodes carries two key risks:

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T., Northrop, G.: Simplify to survive, prescriptive layouts ensure profitable scaling to 32 μm and beyond. In: Proceedings of SPIE, vol. 7275, p. 72750A (March 2009) Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T., Northrop, G.: Simplify to survive, prescriptive layouts ensure profitable scaling to 32 μm and beyond. In: Proceedings of SPIE, vol. 7275, p. 72750A (March 2009)
2.
Zurück zum Zitat Liebmann, L., Baum, Z., Graur, I., Samuels, D.: DFM lessons learned from altPSM design. In: Proceedings of SPIE, 6925, 69250C (2008) Liebmann, L., Baum, Z., Graur, I., Samuels, D.: DFM lessons learned from altPSM design. In: Proceedings of SPIE, 6925, 69250C (2008)
3.
Zurück zum Zitat Perez, V., et al.: Convergent automated chip-level lithography checking and fixing at 45 nm. In: Proceedings of SPIE, 7275 (2009) Perez, V., et al.: Convergent automated chip-level lithography checking and fixing at 45 nm. In: Proceedings of SPIE, 7275 (2009)
4.
Zurück zum Zitat Hui, C., et al.: Hotspot detection and design recommendation using silicon-calibrated CMP model. In: Proceedings of SPIE, 7275 (2009) Hui, C., et al.: Hotspot detection and design recommendation using silicon-calibrated CMP model. In: Proceedings of SPIE, 7275 (2009)
5.
Zurück zum Zitat Liebmann, L.: Layout impact of resolution enhancement techniques: impediment or opportunity? In: ISPD’03, Monterey (2003) Liebmann, L.: Layout impact of resolution enhancement techniques: impediment or opportunity? In: ISPD’03, Monterey (2003)
6.
Zurück zum Zitat Webb, C.: Intel design for manufacturing and evolution of design rules. Proc. SPIE 6925, 692503 (2008)CrossRef Webb, C.: Intel design for manufacturing and evolution of design rules. Proc. SPIE 6925, 692503 (2008)CrossRef
7.
Zurück zum Zitat Pileggi, L., Strojwas, A.J.: Regular fabrics for nano-scaled CMOS technologies. In: Proceedings of ISSCC (2006) Pileggi, L., Strojwas, A.J.: Regular fabrics for nano-scaled CMOS technologies. In: Proceedings of ISSCC (2006)
8.
Zurück zum Zitat Jhaveri, T., et al.: Maximization of layout printability/manufacturability by extreme layout regularity. Micro Nanolithogr. MEMS MOEMS 6(03), 031011–033000 (2007)CrossRef Jhaveri, T., et al.: Maximization of layout printability/manufacturability by extreme layout regularity. Micro Nanolithogr. MEMS MOEMS 6(03), 031011–033000 (2007)CrossRef
9.
Zurück zum Zitat Abercrombie, D., Elakkumanan, P., Liebmann, L.: Restrictive design rules and their impact on 22 nm design and physical verification, EDPS2009 (2009) Abercrombie, D., Elakkumanan, P., Liebmann, L.: Restrictive design rules and their impact on 22 nm design and physical verification, EDPS2009 (2009)
10.
Zurück zum Zitat Volkov, A., Routing Technologies for 28 nm and beyond, Chip Design Magazine, Summer 2011 Volkov, A., Routing Technologies for 28 nm and beyond, Chip Design Magazine, Summer 2011
11.
Zurück zum Zitat White Paper: Tips and techniques for 28 nm design optimization, Altera Corporation, November 2011 White Paper: Tips and techniques for 28 nm design optimization, Altera Corporation, November 2011
12.
Zurück zum Zitat Beylier, C., Moyroud, C., Granger, F.B., Robert, F., Yesilada, E., Trouiller, Y., Marin, J.-C.: Fully integrated litho aware PnR design solution. Proc. SPIE 8327, 83270A (2012)CrossRef Beylier, C., Moyroud, C., Granger, F.B., Robert, F., Yesilada, E., Trouiller, Y., Marin, J.-C.: Fully integrated litho aware PnR design solution. Proc. SPIE 8327, 83270A (2012)CrossRef
13.
Zurück zum Zitat Hurley, P., Kryszczull, K.: Replacing design rules in the VLSI Design Cycle, Proc. of SPIE 8327, 83270B1–B6 (2012)CrossRef Hurley, P., Kryszczull, K.: Replacing design rules in the VLSI Design Cycle, Proc. of SPIE 8327, 83270B1–B6 (2012)CrossRef
14.
Zurück zum Zitat Dai, V., Capodicci, L., Yang, J., Rodriguez, N.: Developing DRC plus through 2D pattern extraction and clustering techniques. Proc. SPIE 7275, 727517 (2009)CrossRef Dai, V., Capodicci, L., Yang, J., Rodriguez, N.: Developing DRC plus through 2D pattern extraction and clustering techniques. Proc. SPIE 7275, 727517 (2009)CrossRef
15.
Zurück zum Zitat Russel, P.: Norvig, Artificial Intelligence. A Modern Approach. Prentice Hall, Englewood Cliffs (1995) Russel, P.: Norvig, Artificial Intelligence. A Modern Approach. Prentice Hall, Englewood Cliffs (1995)
16.
Zurück zum Zitat Duda, R.O., Hart, P.E., Stork, D.G.: Pattern Classification. Wiley, New York (2001)MATH Duda, R.O., Hart, P.E., Stork, D.G.: Pattern Classification. Wiley, New York (2001)MATH
17.
Zurück zum Zitat Mitchell, T.M.: Machine Learning. Mc Graw Hill, New York (1997)MATH Mitchell, T.M.: Machine Learning. Mc Graw Hill, New York (1997)MATH
18.
Zurück zum Zitat Cao, Y., Lu, Y.-W., Chen, L., Ye, J.: Optimized hardware and software for fast, full chip simulation. Proc. SPIE 5754, 407–414 (2005)CrossRef Cao, Y., Lu, Y.-W., Chen, L., Ye, J.: Optimized hardware and software for fast, full chip simulation. Proc. SPIE 5754, 407–414 (2005)CrossRef
19.
Zurück zum Zitat Jang, J.: Manufacturability aware design. Ph.D. thesis, The University of Michigan (2007) Jang, J.: Manufacturability aware design. Ph.D. thesis, The University of Michigan (2007)
20.
Zurück zum Zitat Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press (1998) Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press (1998)
21.
Zurück zum Zitat Pileggi, L., Schmit, H., Strojwas, A.J., et al.: Exploring regular fabrics to optimize the performance-cost trade-off. In: Proceedings of the ACM/IEEE DAC (2003) Pileggi, L., Schmit, H., Strojwas, A.J., et al.: Exploring regular fabrics to optimize the performance-cost trade-off. In: Proceedings of the ACM/IEEE DAC (2003)
22.
Zurück zum Zitat Webb, C.: Layout rule trends and affect upon CPU design, design and process integration for microectronic manufacturing IV. In: Wong, A.K.K., Singh, V.K. (eds) Proceedings of SPIE, 6156, 615602 (2006) Webb, C.: Layout rule trends and affect upon CPU design, design and process integration for microectronic manufacturing IV. In: Wong, A.K.K., Singh, V.K. (eds) Proceedings of SPIE, 6156, 615602 (2006)
23.
Zurück zum Zitat Eclair Pattem Matcher End User’s Guide, Version 5.0, CommandCAD, Inc., March 2006 Eclair Pattem Matcher End User’s Guide, Version 5.0, CommandCAD, Inc., March 2006
24.
Zurück zum Zitat Yang, J., Cohen, E., Tabery, C., Rodriguez, N., Craig, M.: An up-stream design auto-fix flow for manufacturability enhancement. In: 43rd Design Automation Conference (2006) Yang, J., Cohen, E., Tabery, C., Rodriguez, N., Craig, M.: An up-stream design auto-fix flow for manufacturability enhancement. In: 43rd Design Automation Conference (2006)
25.
Zurück zum Zitat Torres, J.A., Berglund, N.C.: Towards manufacturability closure process variations and layout design. In: IEEE EDPS Workshop (2005) Torres, J.A., Berglund, N.C.: Towards manufacturability closure process variations and layout design. In: IEEE EDPS Workshop (2005)
26.
Zurück zum Zitat Torre, J.A.: Litho-friendly design: a necessary complement to RET. Microlithogr. World 15(2), 10–13 (2006). 12-13AMathSciNet Torre, J.A.: Litho-friendly design: a necessary complement to RET. Microlithogr. World 15(2), 10–13 (2006). 12-13AMathSciNet
27.
Zurück zum Zitat Strojwas, A.: Cost effective scaling to 22 nm and below technology nodes. In: VLSI Technology, Systems and Applications, pp 1–2 (2011) Strojwas, A.: Cost effective scaling to 22 nm and below technology nodes. In: VLSI Technology, Systems and Applications, pp 1–2 (2011)
28.
Zurück zum Zitat Hoppe, W., Roessler, T., Torres, J.A.: Beyond rule-based physical verification. In: Proceedings of SPIE, 6349(190) (2006) Hoppe, W., Roessler, T., Torres, J.A.: Beyond rule-based physical verification. In: Proceedings of SPIE, 6349(190) (2006)
29.
Zurück zum Zitat Chiang, C., Kawa, J.: Three DfM challenges: random defects, thickness variation, and printability variation. In: IEEE Asia Pacific Conference on Circuits and Systems, 2006. APCCAS 2006, p.1099, 4–7 Dec 2006 Chiang, C., Kawa, J.: Three DfM challenges: random defects, thickness variation, and printability variation. In: IEEE Asia Pacific Conference on Circuits and Systems, 2006. APCCAS 2006, p.1099, 4–7 Dec 2006
30.
Zurück zum Zitat Peter, K., März, R., Gröndahl, S.: Litho-friendly design (LFD) methodologies applied to library cells. Proc. SPIE 6349(14), 63490E (2006)CrossRef Peter, K., März, R., Gröndahl, S.: Litho-friendly design (LFD) methodologies applied to library cells. Proc. SPIE 6349(14), 63490E (2006)CrossRef
31.
Zurück zum Zitat Capodieci, L.: From optical proximity correction to lithography-driven physical design (1996–2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade, optical microlithography XIX. In: Flagello, D.G. (ed) Proceedings of SPIE, 6154, 615401 (2006) Capodieci, L.: From optical proximity correction to lithography-driven physical design (1996–2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade, optical microlithography XIX. In: Flagello, D.G. (ed) Proceedings of SPIE, 6154, 615401 (2006)
32.
Zurück zum Zitat Gianfagna, M., Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T.: Greg Northrop, Private Communication Gianfagna, M., Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T.: Greg Northrop, Private Communication
33.
Zurück zum Zitat Jang, D. et al.: DFM optimization of standard cells considering random and systematic defect. In: ISOCC (2008) Jang, D. et al.: DFM optimization of standard cells considering random and systematic defect. In: ISOCC (2008)
34.
Zurück zum Zitat Paek, S.W., Kang, J.H., Ha, N., Kim, B.M., Jang, D.H., Jeon, J., Kim, D.W., Chung, K.Y., Yu, S., Park, J.H., Bae s., Song, D., Noh, W., Kim, Y.D., Song, H.S., Choi, H.B., Kim, K.S., Choi, K.M., Choi, W.C., Jeon, J.W., Lee, J.W., Kim, K.S., Park, S.H., Chung, N.Y., Lee, K.D., Hong, Y.K., Kim, B.S.: Yield enhancement with DFM, Design for manufacturability through design-process integration VI. In: Mason, M.E., Sturtevant, J.L. (eds) Proceedings of SPIE, 8327, 832704 (2012) Paek, S.W., Kang, J.H., Ha, N., Kim, B.M., Jang, D.H., Jeon, J., Kim, D.W., Chung, K.Y., Yu, S., Park, J.H., Bae s., Song, D., Noh, W., Kim, Y.D., Song, H.S., Choi, H.B., Kim, K.S., Choi, K.M., Choi, W.C., Jeon, J.W., Lee, J.W., Kim, K.S., Park, S.H., Chung, N.Y., Lee, K.D., Hong, Y.K., Kim, B.S.: Yield enhancement with DFM, Design for manufacturability through design-process integration VI. In: Mason, M.E., Sturtevant, J.L. (eds) Proceedings of SPIE, 8327, 832704 (2012)
36.
Zurück zum Zitat Paek, S.W., Jang, D.H., Park, J.H., Ha, N., Kim, B.M., et al.: Enhanced layout optimization of sub-45 nm standard: memory cells. SPIE, 7725, 72751M (2009) Paek, S.W., Jang, D.H., Park, J.H., Ha, N., Kim, B.M., et al.: Enhanced layout optimization of sub-45 nm standard: memory cells. SPIE, 7725, 72751M (2009)
37.
Zurück zum Zitat Kahng, A.B., Samadi, K.: CMP fill synthesis: a survey of recent studies. IEEE Trans. Comp. Aid. Design 27(1), 3–19 (2008)CrossRef Kahng, A.B., Samadi, K.: CMP fill synthesis: a survey of recent studies. IEEE Trans. Comp. Aid. Design 27(1), 3–19 (2008)CrossRef
38.
Zurück zum Zitat Simmons, M.C., Kang, J.H., Kim, Y., et al.: A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation. SPIE, 7974, 79740M (2011) Simmons, M.C., Kang, J.H., Kim, Y., et al.: A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation. SPIE, 7974, 79740M (2011)
39.
Zurück zum Zitat Ha, N., Lee, J., Paek, S.W. et al.: In-design DFM CMP flow for block level simulation using 32 nm CMP model. SPIE, 7974, 79740W (2011) Ha, N., Lee, J., Paek, S.W. et al.: In-design DFM CMP flow for block level simulation using 32 nm CMP model. SPIE, 7974, 79740W (2011)
40.
Zurück zum Zitat Drennan, P.G., Kniffin, M.L., Locascio, D.R.: Implications of proximity Effects for Analog Design, IEEE CICC (2006) Drennan, P.G., Kniffin, M.L., Locascio, D.R.: Implications of proximity Effects for Analog Design, IEEE CICC (2006)
41.
Zurück zum Zitat Postnikow, S., Hector, S.: ITRS CD error budgets: proposed simulation study methodology. In: International Technology Roadmap for Semiconductors, May (2003) Postnikow, S., Hector, S.: ITRS CD error budgets: proposed simulation study methodology. In: International Technology Roadmap for Semiconductors, May (2003)
42.
Zurück zum Zitat Tabery, C., Page, L.: Use of design pattern layout for automated metrology recipe generation. In: Proceedings of SPIE: Metrology, Inspection and Process Control for Microlithography XIX, vol. 5752, pp. 1424–1434 (2005) Tabery, C., Page, L.: Use of design pattern layout for automated metrology recipe generation. In: Proceedings of SPIE: Metrology, Inspection and Process Control for Microlithography XIX, vol. 5752, pp. 1424–1434 (2005)
43.
Zurück zum Zitat Hook, T., et al.: The dependence of channel length on channel width in narrow-channel CMOS devices for 0.25–0.13 μm technologies. IEEE Electron. Device. Lett. 21(2), 85–87 (2000)CrossRef Hook, T., et al.: The dependence of channel length on channel width in narrow-channel CMOS devices for 0.25–0.13 μm technologies. IEEE Electron. Device. Lett. 21(2), 85–87 (2000)CrossRef
44.
Zurück zum Zitat Su, K.W., et al.: A scalable model for STI mechanical stress effect on layout dependence of MOS electrical characterization. In: IEEE CICC, pp. 245–248 (2003) Su, K.W., et al.: A scalable model for STI mechanical stress effect on layout dependence of MOS electrical characterization. In: IEEE CICC, pp. 245–248 (2003)
45.
Zurück zum Zitat Scott, G., et al.: NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: IEEE IEDM, pp. 827–830 (1999) Scott, G., et al.: NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: IEEE IEDM, pp. 827–830 (1999)
46.
Zurück zum Zitat Bianchi, R.A., et al.: Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: IEEE IEDM, pp. 117–120 (2002) Bianchi, R.A., et al.: Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: IEEE IEDM, pp. 117–120 (2002)
47.
Zurück zum Zitat Miyamoto, M., et al.: Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans. Electron. Devices. 51, 440–443 (2004)CrossRef Miyamoto, M., et al.: Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans. Electron. Devices. 51, 440–443 (2004)CrossRef
48.
Zurück zum Zitat Choi, Y.S., Lian, G., Olubuigde, O., Chung, J., Riley, D., Baldwin, G.: Layout variation Effects in Advanced MOSFECTs: STI-Induced Embedded Sige strain Relaxation and Dual Stress Liner Boundary Proxinuty Effect. IEEE Trans. Electron. Devices. 57(11), 2886–2890 (2010)CrossRef Choi, Y.S., Lian, G., Olubuigde, O., Chung, J., Riley, D., Baldwin, G.: Layout variation Effects in Advanced MOSFECTs: STI-Induced Embedded Sige strain Relaxation and Dual Stress Liner Boundary Proxinuty Effect. IEEE Trans. Electron. Devices. 57(11), 2886–2890 (2010)CrossRef
49.
Zurück zum Zitat Hook, T.H., et al.: Lateral ion implant straggle and mask proximity effect. IEEE Trans. Electron. Devices. 50, 1946–1951 (2003)CrossRef Hook, T.H., et al.: Lateral ion implant straggle and mask proximity effect. IEEE Trans. Electron. Devices. 50, 1946–1951 (2003)CrossRef
50.
Zurück zum Zitat Sheu, Y.M., et al.: Modeling well edge proximity effect on highly-scaled MOSFETs. In: IEEE CICC, pp. 831–834 (2005) Sheu, Y.M., et al.: Modeling well edge proximity effect on highly-scaled MOSFETs. In: IEEE CICC, pp. 831–834 (2005)
51.
Zurück zum Zitat Kumar, D.V., et al.: Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs. IEEE Trans. Electron. Devices 52, 1603–1609 (2005)CrossRef Kumar, D.V., et al.: Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs. IEEE Trans. Electron. Devices 52, 1603–1609 (2005)CrossRef
52.
Zurück zum Zitat Enemon, G., Verheyen, P., De Keersgieter, A., Jurczak, M., de Meyer, K.: Scalability of stress induced by contact-etch-stop layers: a simulation study. IEEE Trans. Electron. Device 54(6), 1446 (2007)CrossRef Enemon, G., Verheyen, P., De Keersgieter, A., Jurczak, M., de Meyer, K.: Scalability of stress induced by contact-etch-stop layers: a simulation study. IEEE Trans. Electron. Device 54(6), 1446 (2007)CrossRef
Metadaten
Titel
DfM at 28 nm and Beyond
verfasst von
Artur Balasinski
Copyright-Jahr
2014
Verlag
Springer New York
DOI
https://doi.org/10.1007/978-1-4614-1761-3_3

Neuer Inhalt