15. Die and Package Level Thermal and Thermal/Moisture Stresses in 3-D Packaging: Modeling and Characterization

3D packaging employing through-silicon vias (TSVs) to connect multiple stacked dies/chips has great potential to achieve high performance and high capacity with low cost and low energy consumption. However, crucial reliability issues often arise in 3D integrated circuits (ICs) packaging due to high thermal stress and moisture stress at both die and package level. In this chapter, TSV related reliability issues such as the measurement of thermal stress in TSV, the effect of thermal stress on carrier mobility and keep-out zone, thermal stress induced via extrusion are illustrated. At the package level, various analytical methods for thermal-stress induced warpage in multi-layered structures are reviewed. The state-of-the-art approaches for warpage control are presented and validated by experimental testing and numerical modeling. Finally, to incorporate moisture stress that comprehends both hygroscopic stress and the pressure of water vapor, a theoretical framework is provided based on damage micromechanics and the effective stress concept. Some case studies are provided to understand the effect of moisture and vapor pressure.