32. DSP–FPGA-Based Parallel Architecture for Acquisition and Compression of Instrumented Pipeline Inspection Gauge Data in Real Time

The paper presents a DSP–FPGA-based parallel architecture for acquisition and compression of data in real time. The architecture is structured with high-performance DSP and acquisition hardware, implemented in FPGA. Hardware blocks for data acquisition with control logics, and FIFO are implemented in FPGA. FIFO interconnects DSP with acquisition hardware, running acquisition task in parallel for achieving maximum throughput. The data compression algorithms based on mean absolute deviation (μAD) is implemented on the DSP. The test results on field data show that the compression algorithm is very effectively implemented with the proposed architecture providing a very high compression ratio. The paper also presents the task management policy for implementing the scheme on DSP–FPGA hardware.