Skip to main content
Erschienen in: Journal of Computational Electronics 3/2019

20.06.2019

Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance

verfasst von: S. V. V. Satyanarayana, Singh Rohitkumar Shailendra, V. N. Ramakrishnan, Sridevi Sriadibhatla

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2019

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based self-controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Hoefflinger, B.: Chips 2020: A Guide to the Future of Nanoelectronics. Springer, New York (2012)CrossRef Hoefflinger, B.: Chips 2020: A Guide to the Future of Nanoelectronics. Springer, New York (2012)CrossRef
2.
Zurück zum Zitat Chen, T.-C.: Overcoming research challenges for CMOS scaling: industry directions. In: 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp. 4–7. IEEE (2006) Chen, T.-C.: Overcoming research challenges for CMOS scaling: industry directions. In: 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp. 4–7. IEEE (2006)
3.
Zurück zum Zitat Sharifi, F., Moaiyeri, M.H., Navi, K., Bagherzadeh, N.: Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron. 14(3), 762–772 (2015)CrossRef Sharifi, F., Moaiyeri, M.H., Navi, K., Bagherzadeh, N.: Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron. 14(3), 762–772 (2015)CrossRef
4.
Zurück zum Zitat Chau, R., Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Majumdar, A., Metz, M., Radosavljevic, M.: Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4(2), 153–158 (2005)CrossRef Chau, R., Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Majumdar, A., Metz, M., Radosavljevic, M.: Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4(2), 153–158 (2005)CrossRef
5.
Zurück zum Zitat Avouris, P.: Electronics with carbon nanotubes. Phys. World 20(3), 40 (2007)CrossRef Avouris, P.: Electronics with carbon nanotubes. Phys. World 20(3), 40 (2007)CrossRef
6.
Zurück zum Zitat Pagiamtzis, K., Sheikholeslami, A.: Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid-State Circuits 41(3), 712–727 (2006)CrossRef Pagiamtzis, K., Sheikholeslami, A.: Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid-State Circuits 41(3), 712–727 (2006)CrossRef
7.
Zurück zum Zitat Kumar, S., Noor, A., Kaushik, B.K., Kumar, B.: Design of ternary content addressable memory (TCAM) with 180 nm. In: 2011 International Conference on Devices and Communications (ICDeCom), pp. 1–5. IEEE (2011) Kumar, S., Noor, A., Kaushik, B.K., Kumar, B.: Design of ternary content addressable memory (TCAM) with 180 nm. In: 2011 International Conference on Devices and Communications (ICDeCom), pp. 1–5. IEEE (2011)
8.
Zurück zum Zitat Chang, Y.-J., Tsai, K.-L., Tsai, H.-J.: Low leakage TCAM for IP lookup using two-side self-gating. IEEE Trans. Circuits Syst. I Regul. Pap. 60(6), 1478–1486 (2013)CrossRef Chang, Y.-J., Tsai, K.-L., Tsai, H.-J.: Low leakage TCAM for IP lookup using two-side self-gating. IEEE Trans. Circuits Syst. I Regul. Pap. 60(6), 1478–1486 (2013)CrossRef
9.
Zurück zum Zitat Lin, S., Kim, Y.-B., Lombardi, F.: Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans. Nanotechnol. 9(1), 30–37 (2010)CrossRef Lin, S., Kim, Y.-B., Lombardi, F.: Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans. Nanotechnol. 9(1), 30–37 (2010)CrossRef
10.
Zurück zum Zitat Kumar, G.S., Singh, A., Raj, B.: Design and analysis of a gate-all-around CNTFET-based SRAM cell. J. Comput. Electron. 17(1), 1–8 (2017) Kumar, G.S., Singh, A., Raj, B.: Design and analysis of a gate-all-around CNTFET-based SRAM cell. J. Comput. Electron. 17(1), 1–8 (2017)
11.
Zurück zum Zitat Das, D., Roy, A., Rahaman, H.: Design of content addressable memory architecture using carbon nanotube field effect transistors. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds.). Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. pp. 233–242. Springer, Berlin, Heidelberg (2012)CrossRef Das, D., Roy, A., Rahaman, H.: Design of content addressable memory architecture using carbon nanotube field effect transistors. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds.). Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. pp. 233–242. Springer, Berlin, Heidelberg (2012)CrossRef
12.
Zurück zum Zitat Nepal, K.: Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. In: 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 421–424. IEEE (2012) Nepal, K.: Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. In: 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 421–424. IEEE (2012)
13.
Zurück zum Zitat Sinha, S.K., Chaudhury, S.: Comparative study of leakage power in CNTFET over MOSFET device. J. Semicond. 35(11), 114002 (2014)CrossRef Sinha, S.K., Chaudhury, S.: Comparative study of leakage power in CNTFET over MOSFET device. J. Semicond. 35(11), 114002 (2014)CrossRef
14.
Zurück zum Zitat Sethi, D., Kaur, M., Singh, G.: Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection. J. Comput. Electron. 16(1), 106–114 (2017)CrossRef Sethi, D., Kaur, M., Singh, G.: Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection. J. Comput. Electron. 16(1), 106–114 (2017)CrossRef
15.
Zurück zum Zitat Kittur, H.M., et al.: Precharge-free, low-power content-addressable memory. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(8), 2614–2621 (2016)CrossRef Kittur, H.M., et al.: Precharge-free, low-power content-addressable memory. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(8), 2614–2621 (2016)CrossRef
16.
Zurück zum Zitat Mahendra, T.V., Mishra, S., Dandapat, A.: Self-controlled high-performance precharge-free content-addressable memory. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(8), 2388–2392 (2017)CrossRef Mahendra, T.V., Mishra, S., Dandapat, A.: Self-controlled high-performance precharge-free content-addressable memory. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(8), 2388–2392 (2017)CrossRef
17.
Zurück zum Zitat Iijima, S.: Helical microtubules of graphitic carbon. Nature 354(6348), 56–58 (1991)CrossRef Iijima, S.: Helical microtubules of graphitic carbon. Nature 354(6348), 56–58 (1991)CrossRef
18.
Zurück zum Zitat Raychowdhury, A., Roy, K.: Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54(11), 2391–2401 (2007)CrossRef Raychowdhury, A., Roy, K.: Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54(11), 2391–2401 (2007)CrossRef
19.
Zurück zum Zitat Hazeghi, A., Krishnamohan, T., Wong, H.-S.P.: Schottky-barrier carbon nanotube field-effect transistor modeling. IEEE Trans. Electron Devices 54(3), 439–445 (2007)CrossRef Hazeghi, A., Krishnamohan, T., Wong, H.-S.P.: Schottky-barrier carbon nanotube field-effect transistor modeling. IEEE Trans. Electron Devices 54(3), 439–445 (2007)CrossRef
20.
Zurück zum Zitat Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.P.: A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—part I: intrinsic elements. IEEE Trans. Electron Devices 62(9), 3061–3069 (2015)CrossRef Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.P.: A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—part I: intrinsic elements. IEEE Trans. Electron Devices 62(9), 3061–3069 (2015)CrossRef
21.
Zurück zum Zitat Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.P.: A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—part II: extrinsic elements, performance assessment, and design optimization. IEEE Trans. Electron Devices 62(9), 3070–3078 (2015)CrossRef Lee, C.-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S.P.: A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—part II: extrinsic elements, performance assessment, and design optimization. IEEE Trans. Electron Devices 62(9), 3070–3078 (2015)CrossRef
22.
Zurück zum Zitat Luo, J., Wei, L., Lee, C.-S., Franklin, A.D., Guan, X., Pop, E., Antoniadis, D.A., Wong, H.-S.P.: Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length. IEEE Trans. Electron Devices 60(6), 1834–1843 (2013)CrossRef Luo, J., Wei, L., Lee, C.-S., Franklin, A.D., Guan, X., Pop, E., Antoniadis, D.A., Wong, H.-S.P.: Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length. IEEE Trans. Electron Devices 60(6), 1834–1843 (2013)CrossRef
23.
Zurück zum Zitat Zhang, Z., Wang, S., Wang, Z., Ding, L., Pei, T., Zhudong, H., Liang, X., Chen, Q., Li, Y., Peng, L.-M.: Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 3(11), 3781–3787 (2009)CrossRef Zhang, Z., Wang, S., Wang, Z., Ding, L., Pei, T., Zhudong, H., Liang, X., Chen, Q., Li, Y., Peng, L.-M.: Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 3(11), 3781–3787 (2009)CrossRef
24.
Zurück zum Zitat d’Honincthun, H.C., Nguyen, H.-N., Galdin-Retailleau, S., Bournel, A., Dollfus, P., Bourgoin, J.P.: Influence of capacitive effects on the dynamic of a CNTFET by Monte Carlo method. Phys. E Low-Dimens. Syst. Nanostruct. 40(7), 2294–2298 (2008)CrossRef d’Honincthun, H.C., Nguyen, H.-N., Galdin-Retailleau, S., Bournel, A., Dollfus, P., Bourgoin, J.P.: Influence of capacitive effects on the dynamic of a CNTFET by Monte Carlo method. Phys. E Low-Dimens. Syst. Nanostruct. 40(7), 2294–2298 (2008)CrossRef
25.
Zurück zum Zitat Seevinck, E., List, F.J., Lohstroh, J.: Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits 22(5), 748–754 (1987)CrossRef Seevinck, E., List, F.J., Lohstroh, J.: Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits 22(5), 748–754 (1987)CrossRef
Metadaten
Titel
Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance
verfasst von
S. V. V. Satyanarayana
Singh Rohitkumar Shailendra
V. N. Ramakrishnan
Sridevi Sriadibhatla
Publikationsdatum
20.06.2019
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2019
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-019-01362-y

Weitere Artikel der Ausgabe 3/2019

Journal of Computational Electronics 3/2019 Zur Ausgabe

Neuer Inhalt