Efficient Design Approaches to Model Ternary D-Flip-Flop and Shift Registers in CNT Technology

The advancement of emerging technologies favors the proliferation of multi-valued logic design as it offers enhancement of circuit performance parameters with increased level of integration. This work has presented carbon nanotube field effect transistor (CNTFET) based ternary shift register designs which are realized by employing single-edge triggered ternary D-flip-flop cells with reset input. The dependency of threshold voltage on carbon nanotube physical dimensions is used for the realization of multiple threshold voltages in ternary logic designs. The D-flip flop design with reset capability implementation is performed using multiplexer based positive and negative latches arranged in master–slave architecture. Further, the D-flip-flop cells with reset input are combined to construct Ternary logic serial input serial output (SISO), parallel input parallel output (PIPO) and parallel input serial output (PISO) registers. The latching of the input across the output happens only if the reset input is high otherwise no latching is performed. The PISO register is operating in two modes of loading and shifting realized using NAND logic. The proposed ternary shift register designs using CNTFETs are simulated using HSPICE considering the 32 nm Stanford CNTFET model. The results demonstrate that for 4-bit register design, power and PDP improvements of more than 70% are achieved for SISO designs and a maximum of 90% is attained for PIPO and PISO register designs as compared to recent counterparts. The Monte-Carlo simulation results indicate robust and stable operation of the proposed designs when subjected to process variations.