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Erschienen in:
2009 | OriginalPaper | Buchkapitel
Efficient K-Means VLSI Architecture for Vector Quantization
verfasst von : Hui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung
Erschienen in: Image Analysis
Verlag: Springer Berlin Heidelberg
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A novel hardware architecture for
k
-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for
k
-means design.