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This book applies to the scientific area of electronic design automation (EDA) and addresses the automatic sizing of analog integrated circuits (ICs). Particularly, this book presents an approach to enhance a state-of-the-art layout-aware circuit-level optimizer (GENOM-POF), by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on the NSGA-II algorithm. The results showed allow the designer to explore the different trade-offs of the solution space, both through the achieved device sizes, or the respective layout solutions.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
This chapter presents a brief introduction to analog integrated circuits (ICs) design and to the area of analog IC design automation. First, the analog IC design problem is presented, that led to the research in this area, then, the traditional analog design flow is sketched and, finally, the features of the proposed methodology to enhance the circuit-sizing task are outlined.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta

Chapter 2. State-of-the-Art on Automatic Analog IC Sizing

Abstract
In this chapter a state-of-the-art review on analog integrated circuit (IC) design automation tools applied to the specification translation problem is presented. Having the right topology for a given set of specifications is indispensable for a high performance design. An inadequate topology makes the design more difficult (or even impossible), and may require unnecessary resources, which is not acceptable in high performance designs. Once the topology is selected, the specifications for the overall block are translated to the specifications for the sub-blocks. The specifications are, in this way, passed through the hierarchy. At the lowest level, the translation reduces to circuit sizing, whereas at the higher levels it produce the sub-blocks performance parameters. In the last years, the scientific community proposed many techniques for the automation of the translation task; some apply only at circuit-level or only at system level, while others apply to both. In this study, several circuit-level sizing techniques are sketched and compared, and then, different model-based optimization approaches are outlined.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta

Chapter 3. Gradient Model Generation

Abstract
This chapter illustrates the Gradient Model generation. The circuit is first sampled using either the Full Factorial or the Fractional Factorial Design of Experiments (DOE) techniques, and then the main effect is used to extract the gradient rules which compose the Gradient Model.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta

Chapter 4. Enhanced AIDA’s Circuit-Level Optimization Kernel

Abstract
This chapter describes how the Gradient Model described in the previous chapter is used to enhance the circuit-level optimization tool, GENOM-POF [1]. GENOM-POF is part of the Analog Integrated circuit Design Automation environment (AIDA) [2], developed in the Integrated Circuits Group at Instituto de Telecomunicações, Lisboa, Portugal. The integration of the gradient model includes both embedding the model in the optimization kernel, and add the model’s setup options to AIDA’s graphical user interface (GUI), which allows the visualization of the results and the configuration of the parameters, such as the objectives, constraints and input variables, ranges, etc.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta

Chapter 5. Results

Abstract
This chapter illustrates the application of the proposed methodology to practical examples. The framework of the proposed methodology for the automatic generation of analog integrated circuits (IC) layout has been coded in JAVA and was executed, for the presented examples, on an Intel® Core™ 2 Quad CPU 2.4 GHz with 6 GB of RAM.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta

Chapter 6. Conclusions and Future Work

Abstract
The proposed methodology for the enhancement of a state-of-the-art circuit-level synthesis approach, GENOM-POF [1], by incorporating a gradient model into a multi-objective multi-constraint optimization kernel was proved by the implementation of a tool, GENOM-POFGM (GENOM-POF + Gradient Model), which is able to generate robust circuit sizing solutions. This chapter presents the closing remarks, and the future directions for the continuous development of GENOM-POFGM.
Frederico A. E. Rocha, Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta
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