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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 4/2018

05.09.2018

Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design

verfasst von: Shashi Bala, Mamta Khosla

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2018

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Abstract

With advantages such as low sub-threshold swing, low OFF-state current and the ability to attain a higher ON–OFF ratio, the tunnel CNTFET is one of the most comprehensively investigated devices for low-power application. The problems associated with this device are fabrication issues since conventional doping is not possible in CNTs. Therefore, a doping-less tunnel CNTFET is proposed which is free from problems associated with a conventional tunnel CNTFET. A mathematical model is developed for an electrostatically doped tunnel CNTFET, and to validate the model accuracy and the equation set, the simulation results are compared with NanoTCAD ViDES results. Finally, the developed model is deployed in an inverter design to verify the suitability of the model for circuit applications.
Vorheriger Artikel Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs
Nächster Artikel Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method

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Metadaten
Titel
Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design
verfasst von
Shashi Bala
Mamta Khosla
Publikationsdatum
05.09.2018
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 4/2018
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-018-1240-7

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