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Über dieses Buch

This book offers readers broad coverage of techniques to model, verify and validate the behavior and performance of complex distributed embedded systems. The authors attempt to bridge the gap between the three disciplines of model-based design, real-time analysis and model-driven development, for a better understanding of the ways in which new development flows can be constructed, going from system-level modeling to the correct and predictable generation of a distributed implementation, leveraging current and future research results.



Chapter 1. Introduction: Modeling, Analysis and Synthesis of Embedded Software and Systems

Embedded systems are increasingly complex, function-rich and required to perform tasks that are mission- or safety-critical. The use of models to specify the functional contents of the system and its execution platform is today the most promising solution to reduce the productivity gap and improve the quality, correctness and modularity of software subsystems and systems. Models allow to advance the analysis, validation, and verification of properties in the design flow, and enable the exploration and synthesis of cost-effective and provably correct solutions. While there is (relative) consensus on the use of models, competing (and not necessarily compatible) approaches are explored in the academic and industrial domain, each with its distinctive features, strengths, and weaknesses. Modeling languages (and the accompanying methodologies) are today roughly divided as belonging to the Model-Based Design (MBD) or Model-Driven Engineering (MDE) approach. Component-based development is a desirable paradigm that applies to both modeling styles. Research work tries to define (and possibly widen) the range of model properties that can be analyzed and demonstrated as correct, providing methods and tools to this purpose. Time properties are an important subset, since they apply to the majority of the complex and distributed systems in the automotive, avionics, and controls domains. A synthesis path, with the methods and tools to generate a (provably correct) software or hardware implementation of a model is a necessary complement to the use of an analyzable modeling language, not only to improve efficiency, but to avoid the introduction of unwanted errors when the model is refined into its implementation.
Alberto Sangiovanni-Vincentelli, Haibo Zeng, Marco Di Natale, Peter Marwedel

Model-Based Design and Synthesis


Chapter 2. Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets

Application advances in the signal processing and communications domains are marked by an increasing demand for better performance and faster time to market. This has motivated model-based approaches to design and deploy such applications productively across diverse target platforms. Dataflow models are effective in capturing these applications that are real-time, multi-rate, and streaming in nature. These models facilitate static analysis of key execution properties like buffer sizes and throughput. There are established tools to generate implementations of these models in software for processor targets. However, prototyping and deployment on hardware targets, in particular reconfigurable hardware such as FPGAs, are critical to the development of new applications. FPGAs are increasingly used in computing platforms for high performance streaming applications. They also facilitate integration with real physical I/O by providing tight timing control and allow the flexibility to adapt to new interface standards. Existing tools for hardware implementation from dataflow models are limited in their ability to combine efficient synthesis and I/O integration and deliver realistic system deployments. To close this gap, we present the LabVIEW DSP Design Module from National Instruments, a framework to specify, analyze, and implement streaming applications on hardware targets. DSP Design Module encourages a model-based design approach starting from streaming dataflow models. The back-end supports static analysis of execution properties and generates implementations for FPGAs. It also includes an extensive library of hardware actors and eases third-party IP integration. Overall, DSP Design Module is an unified design-to-deployment framework that translates high-level algorithmic specifications to efficient hardware, enables design space exploration, and generates realistic system deployments. In this chapter, we illustrate the modeling, analysis, and implementation capabilities of DSP Design Module. We then present a case study to show its viability as a model-based design framework for next generation signal processing and communications systems.
Kaushik Ravindran, Arkadeb Ghosal, Rhishikesh Limaye, Douglas Kim, Hugo Andrade, Jeff Correll, Jacob Kornerup, Ian Wong, Gerald Wang, Guang Yang, Amal Ekbal, Mike Trimborn, Ankita Prasad, Trung N. Tran

Chapter 3. Dataflow-Based, Cross-Platform Design Flow for DSP Applications

Dataflow methods have been widely explored over the years in the digital signal processing (DSP) domain to model, design, analyze, implement, and optimize DSP applications, such as applications in the areas of audio and video data stream processing, digital communications, and image processing. DSP-oriented dataflow methods provide formal techniques that facilitate software design, simulation, analysis, verification, instrumentation and optimization for exploring effective implementations on diverse target platforms. As the landscape of embedded platforms becomes increasingly diverse, a wide variety of different kinds of devices, including graphics processing units (GPUs), multicore programmable digital signal processors (PDSPs), and field programmable gate arrays (FPGAs), must be considered to thoroughly address the design space for a given application. In this chapter, we discuss design methodologies, based on the core functional dataflow (CFDF) model of computation, that help engineers to efficiently explore such diverse design spaces. In particular, we discuss a CFDF-based design flow and associated design methodology for efficient simulation and implementation of DSP applications. The design flow supports system formulation, simulation, validation, cross-platform software implementation, instrumentation, and system integration capabilities to derive optimized signal processing implementations on a variety of platforms. We provide a comprehensive specification of the design flow using the lightweight dataflow (LWDF) and targeted dataflow interchange format (TDIF) tools, and demonstrate it with case studies on CPU/GPU and multicore PDSP designs that are geared towards fast simulation, quick transition from simulation to the implementation, high performance implementation, and power-efficient acceleration, respectively.
Zheng Zhou, Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya

Model-Driven Design, Integration and Verification of Heterogeneous Models


Chapter 4. Model-Driven Design of Software Defined Radio Applications Based on UML

Model-driven design (MDD) is considered a very promising approach to cope with the design of complex software applications such as software defined radio (SDR). This chapter proposes an MDD methodology for SDR applications. Our approach comprises: (1) DiplodocusDF, a domain-specific modelling language for SDR applications, it is a domain specific UML profile. (2) The mechanism to transform DiplodocusDF models into C-language code ready for compilation, and (3) a runtime environment for execution of the generated code. Moreover, the proposed UML profile is supported by TTool, which is a framework for design exploration and formal verification at model level. We illustrate the potential of our methodology designing a SDR application.
Jair Gonzalez, Renaud Pacalet

Chapter 5. On Integrating EAST-ADL and UPPAAL for Embedded System Architecture Verification

Model-based development (MBD) is a common approach adopted in many engineering disciplines for handling complexity. For distributed microprocessor based systems MBD approaches include the use of architecture description languages (ADL’s), modeling and simulation tools and tools for formal verification. To increase their combined effectiveness, the various MBD methods, tools and languages are required to be integrated with each other. This chapter addresses the connection between ADL’s and formal verification in the context of automotive embedded systems. A template-based mapping scheme providing formal interpretation of EAST-ADL, an automotive specific ADL with timed automata (TA) is the main contribution providing a possibility of automated analysis of timing constraints specified for the execution behavior and events of a system. One benefit of using TA is the fact that it can also be used for generating test cases for their usage during late development phases.
Tahir Naseer Qureshi, De-Jiu Chen, Magnus Persson, Martin Törngren

Chapter 6. Schedulability Analysis at Early Design Stages with MARTE

The construction of a design model is a critical phase in real-time systems (RTS) development as the choices made have a direct impact on timing aspects. In traditional model-based approaches, the design relies largely on the designer experience. Once the design model is constructed, a convenient schedulability test has to be found in order to ensure that the design allows the respect of the timing constraints. This late analysis does not guarantee the existence of a test for the given design and does not allow early detection of unfeasible designs. In order to overcome this problem, this chapter proposes the first UML/MARTE methodology for schedulability-aware real-time software design models construction.
Chokri Mraidha, Sara Tucci-Piergiovanni, Sebastien Gerard

Component-Based Design and Real-Time Components


Chapter 7. Early Time-Budgeting for Component-Based Embedded Control Systems

One of the challenging steps in the development of component based embedded control systems involves decomposition of feature or system level timing requirements into component level timing requirements. Often it is observed that the timing is introduced at a later stage in the development cycle and ad hoc estimates are made which lead to costly and multiple design iterations. This chapter proposes a methodology that addresses this problem using a simple but powerful idea of using parametric specification. A key step in the methodology is component time-budgeting, which involves identifying a set of parametric timing requirements for the components realizing a feature functionality. This is followed by a verification step which computes a set of constraints on the parameters such that any valuation of the parameters satisfying the constraints achieves the feature requirements. This avoids the ad hoc time estimates and the consequent design iteration. The methodology is formalized using Parametric Temporal Logic and illustrated on a reasonably sized automotive case study.
Manoj G. Dixit, S. Ramesh, Pallab Dasgupta

Chapter 8. Contract-Based Reasoning for Component Systems with Rich Interactions

In this chapter we propose a rule unifying circular and non-circular assume-guarantee reasoning and show its interest for contract-based design and verification. Our work was motivated by the need to combine, in the top-down methodology of the FP7 SPEEDS project, partial tool chains for two component frameworks derived from the HRC model and using different refinement relations. While the L0 framework is based on a simple trace-based representation of behaviors and uses set operations for defining refinement, the more elaborated L1 framework offers the possibility to build systems of components with complex interactions. Our approach in L1 is based on circular reasoning and results in a method for checking contract dominance which does not require the explicit composition of contracts. In order to formally relate results obtained in L0 and L1, we provide a definition of the minimal concepts required by a consistent contract theory and propose abstract definitions which smoothly encompass hierarchical components. Finally, using our relaxed rule for circular reasoning, we show how to use together the L0 and L1 refinement relations and as a result their respective tool chains.
Susanne Graf, Roberto Passerone, Sophie Quinton

Chapter 9. Extracting End-to-End Timing Models from Component-Based Distributed Embedded Systems

In order to facilitate the end-to-end timing analysis, we present a method to extract end-to-end timing models from component-based distributed embedded systems that are developed using the existing industrial component model, Rubus Component Model (RCM). RCM is used for the development of software for vehicular embedded systems by several international companies. We discuss and solve the issues involved during the model extraction such as extraction of timing information from all nodes and networks in the system and linking of trigger and data chains in distributed transactions. We also discuss the implementation of the method for the extraction of end-to-end timing models in the Rubus Analysis Framework.
Saad Mubeen, Jukka Mäki-Turja, Mikael Sjödin

Timing Analysis and Time-Based Synthesis


Chapter 10. Distributed Priority Assignment in Real-Time Systems

Recent advances in in-system performance analysis allow to determine feasibility of a system configuration within the system itself. Such methods have been successfully used to perform admission control for updates in distributed real-time systems. Parameter synthesis, which is necessary to complement the admission control with self-configuration capabilities, lags behind because current approaches cannot be distributed properly or due to necessary design-time preprocessing steps. In this chapter we present a distributed algorithm to find feasible execution priorities in distributed static-priority-preemptively (SPP) scheduled real-time systems under consideration of end-to-end path latencies. The presented algorithm builds on top of an existing distributed feasibility test, which is derived from compositional performance analysis [1]. With an extensive set of pseudo-randomly generated testcases we demonstrate the applicability of the approach and show that the proposed algorithm can even compete with state-of-the-art design time tools at a fraction of the run time. Thus, despite its application to admission control, the approach is generally applicable to the problem of scheduling priority assignment.
Moritz Neukirchner, Steffen Stein, Rolf Ernst

Chapter 11. Exploration of Distributed Automotive Systems Using Compositional Timing Analysis

This chapter presents a design space exploration method for mixed event-triggered and time-triggered real-time systems in the automotive domain. A design space exploration model is used that is capable of modeling and optimizing state-of-the-art automotive systems including the resource allocation, task distribution, message routing, and scheduling. The optimization is based on a heuristic approach that iteratively improves the system design. Within this iterative optimization it is necessary to analyze each system design where one of the major design objectives that needs to be evaluated is the timing behavior. Since timing analysis is a very complex design task with high computational demands, it might become a bottleneck within the design space exploration. As a remedy, a clustering strategy is presented that is capable of reducing the complexity and minimizing the runtime of the timing analysis. A case study gives evidence of the efficiency of the proposed approach.
Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Samarjit Chakraborty

Chapter 12. Design and Evaluation of Future Ethernet AVB-Based ECU Networks

Due to ever-increasing bandwidth requirements of modern automotive applications, Ethernet AVB is becoming a standard high-speed bus in automotive E/E architectures. Since Ethernet AVB is tailored to audio and video entertainment, existing analysis approaches neglect the specific requirements and features of heterogeneous E/E architectures and their applications. This chapter presents a virtual prototyping approach to consider Ethernet AVB in complex E/E architectures, reflecting key features such as static routing and stream reservation, fixed topology, and real-time applications. A comparison with a timing analysis on case studies from the automotive domain gives evidence that the proposed simulation technique delivers valuable bounds for complete sensor-to-actuator chains, enabling automatic system synthesis and design space exploration approaches.
Michael Glaß, Sebastian Graf, Felix Reimann, Jürgen Teich


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