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14-09-2022

1T-DRAM Cell with Different FET Technologies for Low Power Application

Authors: Durgesh Addala, Sanjeet Kumar Sinha, Mohan Chandu Gadiparthi, Sweta Chander

Published in: Wireless Personal Communications

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Abstract

DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day by day to reach the user's expectation the products are get designed based on low power and portable. The proposed DRAM cell has a separate read and write path for improvement in read and write abilities. Power dissipation is a major issue to solve this issue researchers are focusing on low power circuits and trying to design the circuits with less number of the transistor so that it will consume less amount of power. In this paper, three structures are presently based on MOSFET technology and CNTFET technology. MOSFET model structures are divided into two they are 1.DRAM circuit with Tri-state buffers and 2. DRAM circuit without Tri-state buffers. CNTFET based structure is built with the help of Carbon Nanotube-FET’s and the structure is the same as DRAM without Tri-state buffers. Power analysis, voltage, delay are evaluated with the help of cadence virtuoso and LT spice Tools. The proposed DRAM cell exhibits higher write and reads margins with an improvement compared to conventional cell.
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Metadata
Title
1T-DRAM Cell with Different FET Technologies for Low Power Application
Authors
Durgesh Addala
Sanjeet Kumar Sinha
Mohan Chandu Gadiparthi
Sweta Chander
Publication date
14-09-2022
Publisher
Springer US
Published in
Wireless Personal Communications
Print ISSN: 0929-6212
Electronic ISSN: 1572-834X
DOI
https://doi.org/10.1007/s11277-022-09963-w