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Published in: Journal of Electronic Testing 6/2020

07-12-2020

2019 JETTA-TTTC Best Paper Award

Breeta SenGupta, Dimitar Nikolov, Assmitra Dash and Erik Larsson, “Test Flow Selection for Stacked Integrated Circuits,” Journal of Electronic Testing: Theory and Applications, Volume 35, Number 4, Pages 425–440, August 2019.

Published in: Journal of Electronic Testing | Issue 6/2020

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Excerpt

Abstract: Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture. …

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Metadata
Title
2019 JETTA-TTTC Best Paper Award
Breeta SenGupta, Dimitar Nikolov, Assmitra Dash and Erik Larsson, “Test Flow Selection for Stacked Integrated Circuits,” Journal of Electronic Testing: Theory and Applications, Volume 35, Number 4, Pages 425–440, August 2019.
Publication date
07-12-2020
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 6/2020
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05919-9

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