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Journal of Computational Electronics

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05-09-2018

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

Authors: Suman Kr. Mitra, Brinda Bhowmick

Published in: Journal of Computational Electronics | Issue 4/2018

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Abstract

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.

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Title: A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs
Authors: Suman Kr. Mitra
Brinda Bhowmick
Publication date: 05-09-2018
Publisher: Springer US
Published in: Journal of Computational Electronics / Issue 4/2018
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-018-1236-3

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