A Comparison Analysis of Single-Ended Bit-Line Leakage Reduction Techniques at 40 nm Node

To analyze the single-ended bit-line leakage of SRAM at 40 nm node, two commonly used circuit techniques for reducing single-ended bit-line leakage were compared in this chapter. The first technique is 10T SRAM cell with read-buffer, which inhibits the leakage path from bit-line to ground when word-line is disabled. The experimental results showed that 10T SRAM achieved 3× improvement in bit-line leakage reduction compared to conventional 8T SRAM, but up to 5 orders of magnitude degradation in I _on-to-I _off ratio and less resistant to process variation were obtained. The other technique is Buffer-Foot (Buf-Foot) SRAM, which employs an 8T bit-cell but mitigates bit-line leakage uses peripheral buffer-foot to control the feet of read-buffers, achieving remarkably bit-line leakage reduction. The experimental results showed that the Buf-Foot SRAM exhibited 10–100× improvement in terms of leakage reduction from 1.0 V down to 0.2 V, up to 5 orders of magnitude improvement in I _on-to-I _off ratio, and 17.8× improvement in sensing timing window compared to 8T SRAM, also better tolerance to PVT. So, Buf-Foot SRAM has been founded a more promising solution to reducing bit-line leakage in advanced process technology compared to 10T SRAM.