A Continuous-Time Incremental ΣΔ ADC with Extended Counting Technique

The article presents a comprehensive exploration of a continuous-time incremental sigma-delta ADC with an extended counting technique, focusing on its design, implementation, and performance advantages. It begins by discussing the growing popularity of continuous-time incremental sigma-delta modulators (ISDM) in sensor readout applications, such as biomedical interfaces and audio recording, due to their anti-aliasing filtering capabilities and multiplexing potential. The article then delves into the challenges posed by high oversampling ratios and high-order loop filters, and introduces multi-stage structures as a solution to enhance resolution and efficiency. Among these structures, the extended counting technique is highlighted for its cost-effectiveness and multifaceted benefits, including the elimination of subtractors, better utilization of the linear range of the second-stage quantizer, and independent operation of quantizers. The article provides a thorough analysis of the continuous-time extended counting technique, offering insights into its circuit implementation and proposing a zero-order hold (ZOH) method for discretizing continuous-time integration. It also introduces an auto-tuning circuit to enhance the PVT robustness of the modulator and a charge compensation technique to reduce gain error in the second-stage ADC. The article concludes with a discussion of the measured results, demonstrating the ADC's high precision, low power consumption, and suitability for low-power photocurrent acquisition and multi-channel applications. The article also compares the performance of the proposed ADC with other commonly used ADCs in current sensing systems, highlighting its superior SNDR and Figure of Merit (FoM).