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2024 | OriginalPaper | Chapter

6. A “Digital+CIM” Processor Supporting Large-Scale NN Models

Author : Jinshan Yue

Published in: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Publisher: Springer Nature Singapore

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Abstract

Based on the research work in Chap. 5, this chapter further analyzes the optimization space of “Digital+CIM” NN processors at the system level, and points out the efficiency and accuracy challenges of system-level CIM chips when running large-scale NN applications.

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previous chapter Digital Circuits and CIM Integrated NN Processor

next chapter Summary and Prospect

Yue J, Liu Y, Feng X, He Y, Wang J, Yuan Z, Zhan M, Liu J, Su J-W, Chung Y-L et al (2023) An energy-efficient computing-in-memory NN processor with set-associate blockwise sparsity and ping-pong weight update. IEEE J Sol-State Circ

Si X, Chen J-J, Tu Y-N, Huang W-H, Wang J-H, Chiu Y-C, Wei W-C, Wu S-Y, Sun X, Liu R et al (2019) 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 396–398

Yang J, Kong Y, Wang Z, Liu Y, Wang B, Yin S, Shi L (2019) 24.4 sandwich-RAM: an energy-efficient in-memory BWN architecture with pulse-width modulation. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 394–396

Su J-W, Si X, Chou Y-C, Chang T-W, Huang W-H, Tu Y-N, Liu R, Lu P-J, Liu T-W, Wang J-H et al (2020) 15.2 A 28 nm 64 kB inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 240–242

Si X, Tu Y-N, Huanq W-H, Su J-W, Lu P-J, Wang J-H, Liu T-W, Wu S-Y, Liu R, Chou Y-C et al (2020) 15.5 A 28 nm 64 kB 6T SRAM computing-in-memory macro with 8 b MAC operation for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246–248

Yue J, Yuan Z, Feng X, He Y, Zhang Z, Si X, Liu R, Chang M-F, Li X, Yang H et al (2020) 14.3 A 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter/intra-macro data reuse. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 234–236

Yue J, Feng X, He Y, Huang Y, Wang Y, Yuan Z, Zhan M, Liu J, Su J-W, Chung Y-L et al (2021) 15.2 A 2.75-to-75.9 tops/w computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong cim with simultaneous computation and weight updating. In: 2021 IEEE international solid-state circuits conference (ISSCC), vol 64. IEEE, pp 238–240

Yuan Z, Yue J, Yang H, Wang Z, Li J, Yang Y, Guo Q, Li X, Chang M-F, Yang H et al (2018) STICKER: a 0.41–62.1 TOPS/W 8 bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers. In: 2018 IEEE symposium on VLSI circuits. IEEE, pp 33–34

Yuan Z, Liu Y, Yue J, Yang Y, Wang J, Feng X, Zhao J, Li X, Yang H (2019) STICKER: an energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS. IEEE J Sol-State Circ 55(2):465–477CrossRef

10.

Yuan Z, Yang Y, Yue J, Liu R, Feng X, Lin Z, Wu X, Li X, Yang H, Liu Y (2020) 14.2 A 65 nm 24.7 \(\upmu \)J/frame 12.3 mW activation-similarity-aware convolutional neural network video processor using hybrid precision, inter-frame data reuse and mixed-bit-width difference-frame data codec. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 232–234

11.

Lee J, Kim C, Kang S, Shin D, Kim S, Yoo H-J (2018) UNPU: a 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 218–220

Title: A “Digital+CIM” Processor Supporting Large-Scale NN Models
Author: Jinshan Yue
Publisher: Springer Nature Singapore
Book: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
Print ISBN: 978-981-9734-76-4

Electronic ISBN: 978-981-9734-77-1

Copyright Year: 2024
DOI: https://doi.org/10.1007/978-981-97-3477-1_6