A FPGA Based Two Level Optimized Local Filter Design for High Speed Image Processing Applications

This work presents an efficient Feild Programmable Gate Array (FPGA) based local filter design for portable and high speed image processing applications. It is highly optimized by using two level optimization. The first level optimization at design-level exploits tempo-spatial parallelism of filters by developing parallel/pipelined architecture. For exploiting spatial-parallelism, design computes partial results of multiple MACs in parallel and accumulates them via adder-tree for final result. Though it bears good performance aptitude but adder-tree incurs long critical path (4.713 ns) thus limits design performance. The critical path was reduced to 2.489 ns with temporal parallelism by pipelining the adder-tree. Design performance is further enhanced by deploying the second level optimization at post-implementation level where device aware floor-planning fine tunes the design. It aligns all utilized embedded resources of design on Xilinx Virtex-5 device and confines slice based logic across them. It results in packing the design within small area with reduced slice count and critical path (2.32 ns). After applying two levels of optimization, the design occupies 89 Slices, 3 DSP-Slices, 2 BRAM18 and achieves high frequency of 431.03 MHz.