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A FPGA HardWare Architecture for AZSPWM Based on a Taylor Series Decomposition

  • 2023
  • OriginalPaper
  • Chapter
Published in:
Authors
Andrea Donisi
Luigi Di Benedetto
Rosalba Liguori
Gian Domenico Licciardo
Alfredo Rubino
Published in
Applications in Electronics Pervading Industry, Environment and Society
Publisher
Springer Nature Switzerland

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Abstract

The chapter introduces a pioneering FPGA hardware architecture for Active Zero State Pulse Width Modulation (AZSPWM) in three-phase inverters. By employing Taylor Series decomposition to calculate dwell-times, the architecture avoids the high computational costs associated with trigonometric functions. The proposed design, implemented on a Xilinx Artix VII FPGA, demonstrates superior resource efficiency and lower dynamic power consumption compared to CORDIC and LUT-based architectures. The architecture enables real-time adjustment of the modulation index, making it suitable for applications requiring dynamic control, such as soft start for induction motors. Experimental results validate the architecture's performance, showcasing its potential to revolutionize the control of three-phase power converters.
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previous chapter A Novel Front-End Circuit for the Digital Conversion of QCM-D Responses for FPGA-Based Frequency Measurements
next chapter Analysis, Design and Synthesis of an Execution Tracing Unit (ETU) Based on AUTOSAR Run-Time Interface (ARTI)
Title
A FPGA HardWare Architecture for AZSPWM Based on a Taylor Series Decomposition
Authors
Andrea Donisi
Luigi Di Benedetto
Rosalba Liguori
Gian Domenico Licciardo
Alfredo Rubino
Copyright Year
2023
Book
Applications in Electronics Pervading Industry, Environment and Society

Print ISBN: 978-3-031-30332-6

Electronic ISBN: 978-3-031-30333-3

Copyright Year: 2023

DOI
https://doi.org/10.1007/978-3-031-30333-3_10
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