A high-performance doping-less tunnel FET with pocketed architecture: proposal and analysis

In this paper, we propose a doping-less dual-material double-gate tunnel field-effect transistor with a P⁺ pocket (PP-DMG TFET). This gate-engineered technique is typically used in a MOSFET to improve device performance. The P⁺ pocket is embedded at the source side to enhance the performance of the pocket-engineered PP-DMG TFET device. This paper compares the performance of four DG-TFET-based devices, i.e. single-material gate (SMG), single-material gate with P⁺ pocket (PP-SMG), dual-material gate (DMG), and dual-material gate with P⁺ pocket (PP-DMG), by using 2D simulations. Electrostatic doping based on the charge plasma concept forms the requisite n–i–p⁺ structure for tunneling formed on a thin intrinsic silicon layer. The proposed device (PP-DMG) has high ON-current capability, a high ON/OFF ratio and lower point subthreshold of 15.3 mV/dec, and an average subthreshold of 18.6 mV/dec. The analog parameters transconductance (g_m) and cutoff frequency (f_T) show impressive improvement. The device efficiency and transconductance frequency product (TFP) are also discussed. Finally, linearity and distortion analysis of parameters including VIP2, VIP3, IIP3, and IMD3 is carried out.