A novel design of graphene field-effect transistor-based out-phasing power amplifier

Graphene transistors are promising candidates for nano-circuits in telecommunication bands due to their high amplification bandwidth, extremely high carrier mobility, high saturation velocity, and the good electric conductance of the graphene channel. In this study, the parameters of a compact model are implemented in the Verilog-A language. An out-phasing power amplifier is designed using microstrip input/output matching, bias network, and quarter-wave Chireix divider/combiner over the frequency range of 2–4 GHz. The simulation results of graphene out-phasing power amplifier in advanced design system software show an increase of about 14 dB in the output gain, an intermodulation distortion (IMD) suppression of better than − 21.8 dBc, and a DC power consumption of 20 mW. In addition, the figures of merit of the proposed design show improvements in terms of gain, IMD, power consumption, and input/output return loss compared to other graphene amplifiers at different frequencies. A comparison of our design with some other amplifiers in various technologies at different frequencies shows a good gain and better IMD suppression in our design. Moreover, the power consumption, input/output return loss, and bandwidth of our strategy are relatively improved.