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Arabian Journal for Science and Engineering
Published in: Arabian Journal for Science and Engineering 10/2021

08-04-2021 | Research Article-Electrical Engineering

A Novel Pseudo-Taylor-Exponential Approximation Technique for Input–Output Range Extension with Reduced Linearity Error and its Current-Mode CMOS Implementation

Authors: Pushkar Srivastava, R. K. Sharma

Published in: Arabian Journal for Science and Engineering | Issue 10/2021

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Abstract

A novel mathematical approach has been proposed for input–output range extension of Pseudo-Taylor-Exponential-Approximation (PTEA) for achieving over seven-decade exponential function, while reducing the linearity error by 1 dB and attaining simple coefficients such as to realize this technique in designing the MOSFET based circuit. This new MPTEA technique, has been successfully utilized for its current-mode (I-I) CMOS implementation involving translinear principle of MOSFETs in weak inversion (WI) region. The CMOS synthesis procedure has been detailed and relevant second-order effects consists of noise, bulk-effect etc. have been explored. For post-layout simulations of the synthesized CMOS implementation, the SPECTRE simulation tool from Cadence, with 180 nM CMOS parameters, has been utilized to justify its practical workability. The proposition, in its CMOS layout, occupies an area of 0.0126mm2 only. It consumes only ≈4.92 μW static power by utilizing ± 0.65 V power supply and produces 146.5 dB range of linear-in-dB output with ± 1 dB linearity error.
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Appendix
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Metadata
Title
A Novel Pseudo-Taylor-Exponential Approximation Technique for Input–Output Range Extension with Reduced Linearity Error and its Current-Mode CMOS Implementation
Authors
Pushkar Srivastava
R. K. Sharma
Publication date
08-04-2021
Publisher
Springer Berlin Heidelberg
Published in
Arabian Journal for Science and Engineering / Issue 10/2021
Print ISSN: 2193-567X
Electronic ISSN: 2191-4281
DOI
https://doi.org/10.1007/s13369-021-05495-w

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