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30-06-2022

A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Authors: Ancy Joy, Jinsa Kuruvilla

Published in: Wireless Personal Communications

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Abstract

Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.
Literature
1.
go back to reference Thomas, M.A., Anjana, K., Joy, A., Kuruvilla, J. (2020). Forced-Sleep SVR SRAM for high frequency applications. In  2020 International Conference on Power Electronics and Renewable Energy Applications (PEREA) (pp. 1–5). IEEE. Thomas, M.A., Anjana, K., Joy, A., Kuruvilla, J. (2020). Forced-Sleep SVR SRAM for high frequency applications. In  2020 International Conference on Power Electronics and Renewable Energy Applications (PEREA) (pp. 1–5). IEEE.
2.
go back to reference Golubović, R., Polimeridis, A. G., & Mosig, J. R. (2013). The weighted averages method for semi-infinite range integrals involving products of Bessel functions. IEEE Transactions on Antennas and Propagation, 61(11), 5589–5596. MathSciNetCrossRef Golubović, R., Polimeridis, A. G., & Mosig, J. R. (2013). The weighted averages method for semi-infinite range integrals involving products of Bessel functions. IEEE Transactions on Antennas and Propagation, 61(11), 5589–5596. MathSciNetCrossRef
3.
go back to reference Saxena, N., & Soni, S. (2016). Analysis of different SRAM cell topologies and design of 10T SRAM cell with improved read speed.  Journal of Active & Passive Electronic Devices,  11(1). Saxena, N., & Soni, S. (2016). Analysis of different SRAM cell topologies and design of 10T SRAM cell with improved read speed.  Journal of Active & Passive Electronic Devices11(1).
4.
go back to reference Sanvale, P., Gupta, N., Neema, V., Shah, A. P., & Vishvakarma, S. K. (2019). An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network. Microelectronics Journal, 92, 104611. CrossRef Sanvale, P., Gupta, N., Neema, V., Shah, A. P., & Vishvakarma, S. K. (2019). An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network. Microelectronics Journal, 92, 104611. CrossRef
5.
go back to reference Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., & Xie, Y. (2009). Hybrid cache architecture with disparate memory technologies. ACM SIGARCH Computer Architecture News, 37(3), 34–45. CrossRef Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., & Xie, Y. (2009). Hybrid cache architecture with disparate memory technologies. ACM SIGARCH Computer Architecture News, 37(3), 34–45. CrossRef
6.
go back to reference Prasad, G., & Anand, A. (2015). Statistical analysis of low-power SRAM cell structure. Analog Integrated Circuits and Signal Processing, 82(1), 349–358. CrossRef Prasad, G., & Anand, A. (2015). Statistical analysis of low-power SRAM cell structure. Analog Integrated Circuits and Signal Processing, 82(1), 349–358. CrossRef
7.
go back to reference Kumar, M. K., Noorbasha, F., & Rao, K. S. (2017). Design of low power 16X16 SRAM array using GDI logic with dynamic threshold technique. ARPN Journal of Engineering and Applied Sciences, 12(22), 6571–6576. Kumar, M. K., Noorbasha, F., & Rao, K. S. (2017). Design of low power 16X16 SRAM array using GDI logic with dynamic threshold technique. ARPN Journal of Engineering and Applied Sciences, 12(22), 6571–6576.
8.
go back to reference Pal, S., Bose, S., Ki, W. H., & Islam, A. (2020). A highly stable reliable SRAM cell design for low power applications. Microelectronics Reliability, 105, 113503. CrossRef Pal, S., Bose, S., Ki, W. H., & Islam, A. (2020). A highly stable reliable SRAM cell design for low power applications. Microelectronics Reliability, 105, 113503. CrossRef
9.
go back to reference Pattnaik, G., & Padhy, S. Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept.  International Journal of Computer Applications, 975:8887. Pattnaik, G., & Padhy, S. Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept.  International Journal of Computer Applications, 975:8887.
10.
go back to reference Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories. Wireless Personal Communications, 108(4), 2311–2339. CrossRef Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories. Wireless Personal Communications, 108(4), 2311–2339. CrossRef
11.
go back to reference Pasandi, G., Jafari, M., & Imani, M. (2015). A new low-power 10T SRAM cell with improved read SNM. International Journal of Electronics, 102(10), 1621–1633. Pasandi, G., Jafari, M., & Imani, M. (2015). A new low-power 10T SRAM cell with improved read SNM. International Journal of Electronics, 102(10), 1621–1633.
12.
go back to reference Kumar, C.H., & Kariyappa, B.S. (2018). Design and power analysis of 16 × 16 SRAM Array Employing 7T I-LSVL. In  2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) (pp. 319–322). IEEE. Kumar, C.H., & Kariyappa, B.S. (2018). Design and power analysis of 16 × 16 SRAM Array Employing 7T I-LSVL. In  2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) (pp. 319–322). IEEE.
13.
go back to reference Adithya, S.S.S.N.V., & Basha, D.K. (2020). Full swing 8 × 8 XOR content addressable memory. In  2020 IEEE International Conference for Innovation in Technology (INOCON) (pp. 1–6). IEEE. Adithya, S.S.S.N.V., & Basha, D.K. (2020). Full swing 8 × 8 XOR content addressable memory. In  2020 IEEE International Conference for Innovation in Technology (INOCON) (pp. 1–6). IEEE.
14.
go back to reference Kassa, S.R., & Nagaria, R.K. (2015). A review on robust low power system level digital circuit design approaches in nano-cmos technologies. In  Proceedings of the Sixth International Conference on Computer and Communication Technology 2015 (pp. 371–375). Kassa, S.R., & Nagaria, R.K. (2015). A review on robust low power system level digital circuit design approaches in nano-cmos technologies. In  Proceedings of the Sixth International Conference on Computer and Communication Technology 2015 (pp. 371–375).
15.
go back to reference Ahmad, S., Gupta, M. K., Alam, N., & Hasan, M. (2017). Low leakage single bitline 9 t (sb9t) static random access memory. Microelectronics Journal, 62, 1–11. CrossRef Ahmad, S., Gupta, M. K., Alam, N., & Hasan, M. (2017). Low leakage single bitline 9 t (sb9t) static random access memory. Microelectronics Journal, 62, 1–11. CrossRef
16.
go back to reference Moghaddam, M., Timarchi, S., Moaiyeri, M. H., & Eshghi, M. (2016). An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits, Systems, and Signal Processing, 35(5), 1437–1455. CrossRef Moghaddam, M., Timarchi, S., Moaiyeri, M. H., & Eshghi, M. (2016). An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits, Systems, and Signal Processing, 35(5), 1437–1455. CrossRef
17.
go back to reference Bikki, P., & Karuppanan, P. (2017). SRAM cell leakage control techniques for ultra low power application: A Survey. Circuits and systems, 8(02), 23. CrossRef Bikki, P., & Karuppanan, P. (2017). SRAM cell leakage control techniques for ultra low power application: A Survey. Circuits and systems, 8(02), 23. CrossRef
Metadata
Title
A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis
Authors
Ancy Joy
Jinsa Kuruvilla
Publication date
30-06-2022
Publisher
Springer US
Published in
Wireless Personal Communications
Print ISSN: 0929-6212
Electronic ISSN: 1572-834X
DOI
https://doi.org/10.1007/s11277-022-09865-x