A Variation-Tolerant, Stable, Low-Power 6T SRAM Cell in 32-nm CNTFET Technology

The semiconductor industry is focused on the miniaturization of transistors to achieve smaller VLSI circuits. However, downscaling of CMOS technology presents numerous challenges, including unreliability and high leakage. Consequently, carbon nanotube field-effect transistor (CNTFET) has emerged as a promising alternative to traditional CMOS-based transistors, offering superior properties such as improved current handling characteristics and better gate control. Static random-access memory (SRAM) cells are widely used as cache memory in most of electronic devices, but their repetitive structures result in significant power consumption. This paper introduces a robust, low-power, single-ended 6T (SE6T) SRAM cell with high static noise margins. Simulation results conducted using the Stanford University 32-nm CNTFET technology in the HSPICE simulator, with V_DD = 0.4 V, demonstrate that the proposed SE6T improves RSNM by 1.99 × /3.17 × compared to Conv6T/DCT7T, enhances WSNM by 1.26 × /1.45 × /1.12 × compared to Conv6T/Conv8T/SE8T, and reduces RSNM/WSNM variability by at least 45.24%/41.94%. Regarding power efficiency, the proposed SE6T design shows improvements of 61.82%/50.65%/25.43% in read power compared to Conv6T/DCT7T/SE8T, and reduces write power/leakage power by at least 31.02%/39.33%. Furthermore, the 32-nm CNTFET-based proposed design offers higher robustness, better stability, lower power, and higher speed compared to its 32-nm MOSFET-based counterpart.