Adiabatic CMOS: Limits of Reversible Energy Recovery and First Steps for Design Automation

Standard CMOS technology discards all signal energy during every switching cycle, leading to heat generation that limits the operating speed and the achievable computing performance. Energy-recovery schemes avoid the heat generation, but are often burdened with the cost of significant increase in system complexity and the lack of automated design tools. In this paper, we propose to implement adiabatic CMOS circuits utilizing split-level rails and Bennett clocking, which enable energy-recovery in standard CMOS logic gates with only minor modifications. Using a pessimistic 32 nm bulk MOSFET technology model, a switching energy improvement factor of approximately 10X can be reached over standard CMOS, while we predict that emerging low-leakage transistor technologies potentially enable adiabatic energy improvements up to four orders-of–magnitude over the standard approach. The significant end-result of our method is that we can leverage the huge number of existing standard gate libraries and logic designs for energy-recovery circuits. We outline an approach to integrate the automatic generation of the adiabatic circuits into the standard circuit design flow, including standard gate logic synthesis and place-and-route.