Adiabatic Logic Based Full Adder Design with Leakage Reduction Mechanisms

In this paper, two-phase clocked adiabatic static CMOS logic (2PASCL), stack effect, and body bias techniques have been used for the optimization of a full adder. Based on the above techniques four designs of a full adder, A1 with adiabatic logic, A2 with stack transistor, A3 with body bias, and A4 with stacking + body bias have been implemented. The performance of optimized and existing designs has been evaluated in 0.18 µm CMOS technology. The optimized designs show a significant improvement in power delay product (PDP) in the range of \( \left( {25.33 - 84.49} \right) \times 10^{ - 24}\, {\text{J}} \) for A1, \( \left( {50.21 - 167.32} \right) \times 10^{ - 24}\, {\text{J}} \) for A2, \( \left( {52.65 - 109.16} \right) \times 10^{ - 24} \,{\text{J}} \) for A3 and, \( \left( {36.00 - 81.56} \right) \times 10^{ - 24}\, {\text{J}} \) for A4 as compared to \( \left( {76.14 - 254.03} \right) \times 10^{ - 24} \,{\text{J}} \) of existing 1-bit hybrid full adder with a varying voltage range (1.2–2.8 V), respectively. Simulation results of optimized designs have been compared with the best reported existing designs in literature and optimized designs outperform in terms of PDP with temperature and voltage variations.