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2013 | OriginalPaper | Chapter

14. AES Co-processor

Author : Patrick R. Schaumont

Published in: A Practical Introduction to Hardware/Software Codesign

Publisher: Springer US

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Abstract

In this chapter we will study the implementation of the Advanced Encryption Standard as a hardware accelerator – a hardware module that completes the encryption on behalf of software. We’ll create two implementations: a memory-mapped encryption coprocessor for ARM, and a custom-instruction encryption/decryption implementation for Nios. Both of these cases will highlight the impact of hardware interface design on the overall implementation. The chapter includes important sections of the source code, but these are not fully self-contained. The reader can refer to the book website for a complete set of design files.

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Title: AES Co-processor
Author: Patrick R. Schaumont
Publisher: Springer US
Book: A Practical Introduction to Hardware/Software Codesign
Print ISBN: 978-1-4614-3736-9

Electronic ISBN: 978-1-4614-3737-6

Copyright Year: 2013
DOI: https://doi.org/10.1007/978-1-4614-3737-6_14