Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench | springerprofessional.de

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Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench

Authors: D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

Publisher: Springer US

Book Series : The International Series in Engineering and Computer Science

Included in: Professional Book Archive

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About this book

Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design).

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Table of Contents

Frontmatter

1. Introduction

Abstract

Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

2. Design Representations and Synthesis

Abstract

Before describing each of the Workbench design tools in detail, it is important to understand both the conceptual and detailed models of design representation used by the tools. This chapter presents the Workbench’s models of design representation, and with this background, defines the synthesis steps implemented by the Workbench tools.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

3. Transformations

Abstract

As a first step in algorithmic synthesis, the designer may want to transform or partition the design, either to improve its efficiency or to explore design alternatives. At the Algorithmic Level, the design can be behaviorally partitioned into concurrent processes and pipestages, or can be structurally partitioned across two or more chips or boards. At the Register-Transfer Level, the design can be transformed to allow the control step scheduler and data path allocator to obtain a more efficient implementation. This chapter describes some of the transformations implemented in the Workbench.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

4. Architectural Partitioning (APARTY)

Abstract

Architectural partitioning is an early step in the Algorithmic Level synthesis process. It divides the behavior among high level physical units such as VLSI chips. There are several reasons for including this phase in the design process. One of the difficulties of synthesis is the lack of information in the behavioral description about physical aspects of the design that would aid in making decisions about the translation to the structural domain. This difficulty is compounded by the interdependency of design decisions. Architectural Partitioning addresses these problems by extracting high level structural information from a behavioral description. This information can be used in the synthesis process not only by giving preliminary clues about how synthesis should progress, but also by providing a global goal that can be used to maintain consistency across different design phases and allowing for a high level exploration of the design space early in the synthesis process.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

5. Control Step Scheduling (CSTEP)

Abstract

Scheduling assigns operators in the behavioral specification to control steps that represent clock cycles in the completed design. Because scheduling and other design tasks are heavily interdependent, it has been recognized as an important part of the synthesis problem [Gajski86]. When interface information is added to the synthesis problem, scheduling becomes even more important because it determines whether timing constraints can be met in the resulting implementation.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

6. Data Path Allocation (EMUCS)

Abstract

Data path allocation encompasses several steps of the design process: the allocation of hardware, the binding of data flow operators and values to that hardware, and the appropriate interconnection of the hardware to realize the data-flow. The hardware allocated is at the functional block level and includes modules such as registers, functional units, and multiplexors. In general, Value Trace operators are bound to functional units, VT values are bound to registers or wires, and multiplexors and busses are used to steer data flow among the other components. The goal of data path allocation is to build a functional block level design that is both small and easily realizable with respect to the target technology.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

7. Microprocessor Synthesis (SUGAR)

Abstract

The four previous chapters describe one approach to Algorithmic and Register-Transfer level synthesis. In contrast to these four separate design tools that work together, the SUGAR microprocessor synthesis tool combines elements of each of these tools. This chapter will highlight three issues in register-transfer synthesis by discussing how the organization of SUGAR differs from the previous approach. The issues are: how to handle interactions between the design steps and substeps in algorithmic and register-transfer level synthesis, the differences between style-specific and general-purpose synthesis methods, and the role of knowledge representation methods.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

8. Synthesis Results

Abstract

Designs for five architectures are presented in this chapter to illustrate the range of capabilities of the synthesis tools in the Workbench. The designs, summarized in Table 8–1, are listed in order of increasing complexity. The first 4 architectures, the Elliptical Filter, the Kalman Filter, the BTL310, and the MCS6502 were synthesized using various design exploration options in the general synthesis path. The last two architectures, the MCS6502 and the Motorola 68000 are both microprocessors. The MCS6502 was synthesized through both the general and style specific paths. The 68000 is too big for the general path, but a portion of its capabilities was synthesized by SUGAR.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

8. Correlating the Multilevel Design Representation (CORAL)

Abstract

Previous chapters have discussed the actual process of synthesizing a structural design from a behavioral description. This chapter offers a method of preserving design information during that process. One of the problems encountered in many automated synthesis systems is that no information is provided describing the relationships between the various intermediate representations of the design that exist in the system. One feeds a design specification into the system and receives an implementation, but the system does not describe the relationship between the input and output design representations.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

10. Observations and Future Work

Abstract

While the research projects presented here combine to demonstrate Algorithmic and Register-Transfer Level Synthesis, they are far from the final solution. Rather they each have served to demonstrate basic concepts and approaches to the steps in synthesis, and together have shown two methods of integrating the steps into a synthesis system. In this Chapter, we make observations based on the results of the synthesis programs presented in the previous chapters and suggest future work in the area.

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn

Backmatter

Title: Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
Authors: D. E. Thomas
E. D. Lagnese
R. A. Walker
J. A. Nestor
J. V. Rajan
R. L. Blackburn
Copyright Year: 1990
Publisher: Springer US
Electronic ISBN: 978-1-4613-1519-3
Print ISBN: 978-1-4612-8815-2
DOI: https://doi.org/10.1007/978-1-4613-1519-3