Ambient Communications and Computer Systems

Table of Contents

1. Frontmatter

2. Intelligent Hardware and Software Design

   1. Frontmatter

   2. Lion Algorithm: A Nature-Inspired Algorithm for Generation Rescheduling-Based Congestion Management

      Pawan C. Tapre, Dharmendra Kumar Singh, Sudhir Paraskar

      Abstract

      The practitioners and researchers have received considerable attention solving complex optimization problems with meta-heuristic algorithms during the past decade. Many of these algorithms are inspired by various phenomena of nature. One of the promising solutions for secure and continuous power flow in the transmission line is rescheduling-based congestion management approach, but the base problem is rescheduling cost. To solve the congestion with minimized rescheduling cost, a new population-based algorithm, the Lion Algorithm (LA), is introduced in this paper. The basic motivation for development of this optimization algorithm is based on special lifestyle of lions and their cooperation characteristics. Based on some benchmark, Lion Algorithm (LA) is compared with the existing conventional algorithms such as particle swarm optimization (PSO), genetic algorithm (GA), artificial bee colony (ABC) and firefly (FF) by analysing the convergence, cost and congestion. In IEEE 30 bus system, experimental investigation is carried out and the obtained results by the proposed algorithm Lion Algorithm (LA) in comparison with the other algorithms used in this paper.

   3. A Dual-Coding Technique to Reduce Dynamic Power Dissipation in Deep Submicron (DSM) Technology

      Tanu Verma

      Abstract

      In a typical bus system, 10% of the power dissipation is static or leakage and 90% is dynamic power. Hence, dynamic power dissipation reduction is main objective of our current research work. In our current research work, power dissipation is reduced in deep submicron (DSM) technology. It has been found that 75% of dynamic power dissipation is due to coupling transitions, whereas only 25% is due to self-transitions. This paper develops a novel technique, dual coding algorithm, in which inter-wire capacitance considers sufficiently and reduces the average power dissipation due to coupling transition approximately up to 50–66.66% with an additional area penalty. The effectiveness of coding method has been tested using MATLAB. Transmission results are tested on bus of system on chip which is simulated on Xilinx and implemented on FPGA.

   4. Short-Term Solar Power Forecasting Using Random Vector Functional Link (RVFL) Network

      Arpit Aggarwal, M. M. Tripathi

      Abstract

      Accurate solar power forecasting greatly influences the planning processes undertaken in operation centres of energy providers that relate to actual solar power generation, distribution, system maintenance and pricing. This paper compares the performance of three networks, namely single shrouded layer feed-forward neural network (SLFN), random weight single shrouded layer feed-forward neural network (RWSLFN) and random vector functional link (RVFL) network on the solar power data of Sydney, Australia, of the year 2015 for day and week ahead solar power forecasting. We show that the introduced scheme may adequately learn hidden patterns and accurately determine the solar power forecast by utilizing a range of heterogeneous sources of input that relate not necessarily with the measurement of solar power itself but also other parameters such as effects of temperature, humidity, time and wind speed. The effect of input–output connections is studied, and it is found out that RWSLFN with direct input–output connections also known as RVFL performs better than other RWSLFNs and SLFNs.

   5. A CSA-Based Architecture of Vedic Multiplier for Complex Multiplication

      Tapsi Gupta, Janki Ballabh Sharma

      Abstract

      The critical process in modern digital signal processing systems is complex multiplication. The speed and complexity of overall system depend upon complex multipliers. In this paper, a multi-operand carry-save adder (CSA)-based Vedic multiplier for complex multiplication is proposed. The proposed Vedic multiplier is based on Urdhva Tiryakbhyam Sutra of Vedic mathematics. For the improvement in the performance of the proposed Vedic multiplier architecture, CSA and Binary to Excess-1 code converters are used. Proposed \(32 \times 32\) bit Vedic multiplier, \(64 \times 64\) bit Vedic multiplier and complex multiplier architectures are implemented using VHDL in Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with the conventional booth and array multiplier-based architectures, which shows that the proposed scheme provides improved delay, low hardware (LUTs) and low complexity. Due to higher bit multiplication rate and low power dissipation, the proposed architecture is useful for modern wireless communication applications.

   6. Design and Analysis of 8-Bit Carry Look-Ahead Adder Using CMOS and ECRL Technology

      Shilpa Ameta, Vijendra Maurya, Ashik Hussain, Navneet Agrawal

      Abstract

      Full adders are the building blocks of nearly all the VLSI applications—be it digital signal processing or image and video processing. In this paper, an 8-bit Carry Look-ahead Adder is implemented and compared using two different types of designs—a conventional Complementary Metal-Oxide Semiconductor (CMOS) logic and an Efficient Charge Recovery Logic (ECRL). These adders are designed and simulated using Tanner Tools v15.23 with 180 nm technology. Performance parameters like power consumption and propagation delay are compared by varying input supply and operating frequency for the two different circuits. The comparison shows that an 8-bit CLA design using ECRL Adiabatic logic is better than an 8-bit CLA design using CMOS logic in terms of power consumption, transistor count, and power delay product (PDP).

   7. Enhancement of Microstrip Patch Antenna Parameters Using Defective Ground Structure

      Mahesh K. Pote, Prachi Mukherji

      Abstract

      Microstrip patch antenna is used with defective ground structure (DGS). In DGS, various types of defects can be made on the ground plane. The improved microstrip patch antenna (MPA) with enhanced parameters is proposed in this paper. The first design implemented is without DGS, the second design is with one slot of rectangular shape on the ground plane, and the third design is with two slots of rectangular shape on the ground plane. To improve return loss, VSWR, bandwidth of the proposed antennas, optimization of the antenna design parameters has been carried out using High Frequency Structure Simulator software. Microstrip patch antenna has been very popular due to its small size, lightweight, low profile, and less cost. Three designs are compared in this paper; the third design with two rectangular DGS slots is giving improved return loss, VSWR, bandwidth.

   8. Adaptive Neural Type II Fuzzy Logic-Based Speed Control of Induction Motor Drive

      Shoeb Hussain, Mohammad Abid Bazaz

      Abstract

      An adaptive neural type II fuzzy logic control (FLC) is designed for control of speed of induction motor in this paper. Intelligent control has improved the performance of vector-controlled drives compared to the conventional PI controller (PIC). Type I FLC eliminates the problems of PIC, but certain uncertainties remain in the system that needs to be effectively tackled with. As such, type II FLC controller is implemented for controlling the speed of drive. Herein, an adaptive controller is designed with neural network determining the rules for the type II FLC. Controller thus results in reduced torque pulsations and lesser current harmonics. Simulation is carried out in MATLAB on the induction motor drive utilizing the controller proposed in the paper, and results are compared with those obtained using PIC.

   9. Hybrid Methodology for Optimal Allocation of Synchronous Generator-Based DG

      Navdeep Kaur, Sanjay Kumar Jain

      Abstract

      In this paper, a hybrid methodology is implemented for optimal allocation of synchronous generator-based dispersed generation, for minimization of power losses in distribution system considering voltage dependent practical loads. The proposed hybrid approach is a combination of equivalent current injection-based sensitivity factor and particle swarm optimization. Sensitivity factors advantages in reducing the search space and optimal allocation of synchronous generator-based DG are obtained by particle swarm optimization for the diminution of power losses. The suggested method is validated on 33-bus and 69-bus radial distribution system. The results show significant improvement in voltage profile of all buses after optimal allocation of DG in distribution system.

   10. Enhanced Navigation Cane for Visually Impaired

       R. Akhil, M. S. Gokul, Sarang Sanal, V. K. Sruthi Menon, Lekshmi S. Nair

       Abstract

       Vision is an important aspect of brain functionality as it allows us to view our surroundings, and maintain the incisiveness of our mind. For a blind person, to walk without resistance, is the most difficult task. Visually impaired are compelled to depend on others for conducting daily activities, especially walk outdoor. As a humanitarian service, our paper aims to help the blind people to walk independently and enjoy the freedom of walking. The model we present here act as a virtual eye to the visually disabled persons, which helps them to navigate to their destinations without the help of others. This model uses a mobile app, concurrent with the lately developed system using the fundamental principles of Arduino Uno board is based on ATmega328 microcontroller. This module is appended to a walking stick so that it is manageable by a blind person. The sensor in the apparatus returns the span warns with a sound alert if any target can be deleterious to the blind person. The system brings a new domain, Internet of Things (IoT), to the fore of the blind people, to make their existence uncomplicated.