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2020 | OriginalPaper | Chapter

An Approach: Applicability of Existing Heterogeneous Multicore Real-Time Task Scheduling in Commercially Available Heterogeneous Multicore Systems

Authors : Kalyan Baital, Amlan Chakrabarti

Published in: Data Management, Analytics and Innovation

Publisher: Springer Singapore

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Abstract

Interest in design and use of heterogeneous multicore architectures has been increased in recent years due to the fact that the energy optimization and parallelization in heterogeneous multicore architecture are better than that of homogeneous multicore architecture. In heterogeneous multicore architectures, cores have similar Instruction Set Architecture (ISA) but the characteristics of the cores are different with respect to power and performance. Hence, heterogeneous architecture provides new prospects for energy-efficient computation and parallelization. Heterogeneous systems, furnished with different types of cores provide the mechanism to take actions with respect to irregular communication patterns, energy efficiency, high parallelism, load balancing, and unexpected behaviors. However, designing such heterogeneous systems for the different platforms like cloud, Internet of Things (IoT), Smart Devices, and Embedded Systems is still challenging. This paper studies the commercially available heterogeneous multicore architectures and finds out an approach or method to apply the existing work on heterogeneous multicore real-time task scheduling model to commercially available heterogeneous multicore architecture to achieve the parallelism, load balancing, and maximum throughput. The paper shows that the approach can be applied very efficiently to some of the commercially available heterogeneous systems to establish a generic heterogeneous model for the platforms like cloud, Internet of Things (IoT), Smart Devices, Embedded Systems, and other application areas.

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Literature
1.
go back to reference Baital, K., Chakrabarti, A.: Dynamic scheduling of real-time tasks in heterogeneous multicore systems. IEEE Embed. Syst. Lett. 11(1), 29–32 (2019) CrossRef Baital, K., Chakrabarti, A.: Dynamic scheduling of real-time tasks in heterogeneous multicore systems. IEEE Embed. Syst. Lett. 11(1), 29–32 (2019) CrossRef
2.
go back to reference Jha, S., He, B., Lu, M., Cheng, X., Huynh, H.P.: Improving main memory hash joins on Intel Xeon Phi processors: an experimental approach. Proc. VLDB Endow. 8(6), 642–653 (2015)CrossRef Jha, S., He, B., Lu, M., Cheng, X., Huynh, H.P.: Improving main memory hash joins on Intel Xeon Phi processors: an experimental approach. Proc. VLDB Endow. 8(6), 642–653 (2015)CrossRef
3.
go back to reference Reinders, J.: An Overview of Programming for Intel® Xeon® processors and Intel® Xeon Phi™ Coprocessors, pp. 1–21. Intel Corporation, Santa Clara (2012) Reinders, J.: An Overview of Programming for Intel® Xeon® processors and Intel® Xeon Phi™ Coprocessors, pp. 1–21. Intel Corporation, Santa Clara (2012)
4.
go back to reference Fang, J., Sips, H., Zhang, L., Xu, C., Varbanescu, A.L.: Test-Driving Intel Xeon Phi. In: Proceedings of 5th ACM/SPEC International Conference on Performance Engineering, NY, USA, 2014, pp. 137–148 Fang, J., Sips, H., Zhang, L., Xu, C., Varbanescu, A.L.: Test-Driving Intel Xeon Phi. In: Proceedings of 5th ACM/SPEC International Conference on Performance Engineering, NY, USA, 2014, pp. 137–148
5.
go back to reference Coviello, G., Cadambi, S., Chakradhar, S.: A coprocessor sharing-aware scheduler for Xeon Phi-based compute clusters. In: Proceedings of IEEE 28th International Parallel and Distributed Processing Symposium, Phoenix, AZ, 2014, pp. 337–346 Coviello, G., Cadambi, S., Chakradhar, S.: A coprocessor sharing-aware scheduler for Xeon Phi-based compute clusters. In: Proceedings of IEEE 28th International Parallel and Distributed Processing Symposium, Phoenix, AZ, 2014, pp. 337–346
6.
go back to reference Miyamoto, T., Ishizaka, K., Hosomi, T.: A dynamic offload scheduler for spatial multitasking on Intel Xeon Phi coprocessor. In: Proceedings of SASIMI 2013, pp. 261–266 Miyamoto, T., Ishizaka, K., Hosomi, T.: A dynamic offload scheduler for spatial multitasking on Intel Xeon Phi coprocessor. In: Proceedings of SASIMI 2013, pp. 261–266
7.
go back to reference Hirokawa, Y., Boku, T., Sato, S.A., Yabana, K.: Electron dynamics simulation with time-dependent density functional theory on large scale symmetric mode Xeon Phi cluster. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Chicago, IL, 2016, pp. 1202–1211 Hirokawa, Y., Boku, T., Sato, S.A., Yabana, K.: Electron dynamics simulation with time-dependent density functional theory on large scale symmetric mode Xeon Phi cluster. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Chicago, IL, 2016, pp. 1202–1211
8.
go back to reference Lan, H., Liu, W., Schmidt, B., Wang, B.: Accelerating large-scale biological database search on xeon phi-based neo-heterogeneous architectures. In: Proceedings of IEEE International Conference on Bioinformatics and Biomedicine (BIBM), Washington, DC, 2015, pp. 503–510 Lan, H., Liu, W., Schmidt, B., Wang, B.: Accelerating large-scale biological database search on xeon phi-based neo-heterogeneous architectures. In: Proceedings of IEEE International Conference on Bioinformatics and Biomedicine (BIBM), Washington, DC, 2015, pp. 503–510
9.
go back to reference Gerangelos, S., Koziris, N.: vPHI: enabling xeon phi capabilities in virtual machines. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lake Buena Vista, FL, 2017, pp. 1333–1340 Gerangelos, S., Koziris, N.: vPHI: enabling xeon phi capabilities in virtual machines. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lake Buena Vista, FL, 2017, pp. 1333–1340
10.
go back to reference Chen, S., Senar, M.A.: Improving performance of genomic aligners on intel xeon phi-based architectures. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Vancouver, BC, 2018, pp. 570–578 Chen, S., Senar, M.A.: Improving performance of genomic aligners on intel xeon phi-based architectures. In: Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Vancouver, BC, 2018, pp. 570–578
11.
go back to reference Xie, B., Liu, X., Zhan, J., Jia, Z., Zhu, Y., Wang, L., Zhang, L.: Characterizing data analytics workloads on Intel Xeon Phi. In: Proceedings of IEEE International Symposium on Workload Characterization, Atlanta, GA, 2015, pp. 114–115 Xie, B., Liu, X., Zhan, J., Jia, Z., Zhu, Y., Wang, L., Zhang, L.: Characterizing data analytics workloads on Intel Xeon Phi. In: Proceedings of IEEE International Symposium on Workload Characterization, Atlanta, GA, 2015, pp. 114–115
12.
go back to reference Nookala, P., Dimitropoulos, S., Stough, K., Raicu, I.: Evaluating the support of MTC applications on Intel Xeon Phi many-core accelerators. In: Proceedings of IEEE International Conference on Cluster Computing, Chicago, IL, 2015, pp. 510–511 Nookala, P., Dimitropoulos, S., Stough, K., Raicu, I.: Evaluating the support of MTC applications on Intel Xeon Phi many-core accelerators. In: Proceedings of IEEE International Conference on Cluster Computing, Chicago, IL, 2015, pp. 510–511
13.
go back to reference Pennycook, S.J., Hughes, C.J., Smelyanskiy, M., Jarvis, S.A.: Exploring SIMD for molecular dynamics, using Intel Xeon processors and Intel Xeon Phi coprocessors. In: Proceedings of IEEE 27th International Symposium on Parallel and Distributed Processing, Boston, MA, 2013, pp. 1085–1097 Pennycook, S.J., Hughes, C.J., Smelyanskiy, M., Jarvis, S.A.: Exploring SIMD for molecular dynamics, using Intel Xeon processors and Intel Xeon Phi coprocessors. In: Proceedings of IEEE 27th International Symposium on Parallel and Distributed Processing, Boston, MA, 2013, pp. 1085–1097
14.
go back to reference Misra, S., Pamnany, K., Aluru, S.: Parallel mutual information based construction of genome-scale networks on the Intel Xeon Phi™ coprocessor. In: IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 12, no. 5, pp. 1008–1020, 1 September–October 2015CrossRef Misra, S., Pamnany, K., Aluru, S.: Parallel mutual information based construction of genome-scale networks on the Intel Xeon Phi™ coprocessor. In: IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 12, no. 5, pp. 1008–1020, 1 September–October 2015CrossRef
15.
go back to reference Gao, C., Gutierrez, A., Rajan, M., Dreslinski, R.G., Mudge, T., Wu, C.: A study of mobile device utilization. In: Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA, 2015, pp. 225–234 Gao, C., Gutierrez, A., Rajan, M., Dreslinski, R.G., Mudge, T., Wu, C.: A study of mobile device utilization. In: Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA, 2015, pp. 225–234
16.
go back to reference Butko, A., Bruguier, F., Gamatie, A., Sassatelli, G., Novo, D., Torres, L., Robert, M.: Full-system simulation of big.LITTLE multicore architecture for performance and energy exploration. In: Proceedings of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), Lyon, France, 2016, pp. 201–208 Butko, A., Bruguier, F., Gamatie, A., Sassatelli, G., Novo, D., Torres, L., Robert, M.: Full-system simulation of big.LITTLE multicore architecture for performance and energy exploration. In: Proceedings of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), Lyon, France, 2016, pp. 201–208
17.
go back to reference Greenhalgh, P.: big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7, ARM White Paper, 2011, pp. 1–8 Greenhalgh, P.: big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7, ARM White Paper, 2011, pp. 1–8
18.
go back to reference Jeff, B.: big.LITTLE technology moves towards fully heterogeneous global task scheduling, ARM White Paper, 2013, pp. 1–13 Jeff, B.: big.LITTLE technology moves towards fully heterogeneous global task scheduling, ARM White Paper, 2013, pp. 1–13
19.
go back to reference ARM White Paper: big.LITTLE Technology: The Future of Mobile, 2013, pp. 1–12 ARM White Paper: big.LITTLE Technology: The Future of Mobile, 2013, pp. 1–12
20.
go back to reference Kamdar, S., Kamdar, N.: big.LITTLE architecture: heterogeneous multicore processing. Int. J. Comput. Appl. 119(1), 35–38 (2015) Kamdar, S., Kamdar, N.: big.LITTLE architecture: heterogeneous multicore processing. Int. J. Comput. Appl. 119(1), 35–38 (2015)
21.
go back to reference Yu, K., Han, D., Youn, C., Hwang, S., Lee, J.: Power-aware task scheduling for big.LITTLE mobile processor. In: Proceedings of International SoC Design Conference (ISOCC), Busan, 2013, pp. 208–212 Yu, K., Han, D., Youn, C., Hwang, S., Lee, J.: Power-aware task scheduling for big.LITTLE mobile processor. In: Proceedings of International SoC Design Conference (ISOCC), Busan, 2013, pp. 208–212
22.
go back to reference Jain, S., Navale, H., Ogras, U., Garg, S.: Energy efficient scheduling for web search on heterogeneous microservers. In: Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Rome, 2015, pp. 177–182 Jain, S., Navale, H., Ogras, U., Garg, S.: Energy efficient scheduling for web search on heterogeneous microservers. In: Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Rome, 2015, pp. 177–182
23.
go back to reference Nishtala, R., Carpenter, P., Petrucci, V., Martorell, X.: Hipster: hybrid task manager for latency-critical cloud workloads. In: Proceedings of IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 409–420 Nishtala, R., Carpenter, P., Petrucci, V., Martorell, X.: Hipster: hybrid task manager for latency-critical cloud workloads. In: Proceedings of IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 409–420
24.
go back to reference Holmgren, R.: Energy efficiency experiments on Samsung Exynos 5 heterogeneous multicore using OmpSs task based programming. MS Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, pp. 1–55 (2015) Holmgren, R.: Energy efficiency experiments on Samsung Exynos 5 heterogeneous multicore using OmpSs task based programming. MS Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, pp. 1–55 (2015)
25.
go back to reference Yoo, S., Shim, Y., Lee, S., Lee, S., Kim, J.: A case for bad big.LITTLE switching: how to scale power-performance in SI-HMP. In: Proceedings of HotPower’15 ACM Proceedings of the Workshop on Power-Aware Computing and Systems, NY, USA, 2015, pp. 1–5 Yoo, S., Shim, Y., Lee, S., Lee, S., Kim, J.: A case for bad big.LITTLE switching: how to scale power-performance in SI-HMP. In: Proceedings of HotPower’15 ACM Proceedings of the Workshop on Power-Aware Computing and Systems, NY, USA, 2015, pp. 1–5
26.
go back to reference Villebonnet, V., Costa, G.D., Lefevre, L., Pierson, J., Stolf, P.: Towards generalizing “big.Little” for energy proportional HPC and cloud infrastructures. In: Proceedings of IEEE Fourth International Conference on Big Data and Cloud Computing, Sydney, NSW, 2014, pp. 703–710 Villebonnet, V., Costa, G.D., Lefevre, L., Pierson, J., Stolf, P.: Towards generalizing “big.Little” for energy proportional HPC and cloud infrastructures. In: Proceedings of IEEE Fourth International Conference on Big Data and Cloud Computing, Sydney, NSW, 2014, pp. 703–710
Metadata
Title
An Approach: Applicability of Existing Heterogeneous Multicore Real-Time Task Scheduling in Commercially Available Heterogeneous Multicore Systems
Authors
Kalyan Baital
Amlan Chakrabarti
Copyright Year
2020
Publisher
Springer Singapore
DOI
https://doi.org/10.1007/978-981-32-9949-8_8