An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder

Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting success. The introduced architecture is robust where the explicit design of full adder and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In proposed Ex-OR design, first output is received with no any latency which can be a suitable design for implementation of the high-speed full adder design. In addition, power estimation results are obtained after simulation of proposed designs in QCAPro tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.