An Optimized Hardware Neural Network Design Using Dynamic Analytic Regulated Configuration

Due to the inherent parallelism offered by the Artificial Neural Networks (ANNs) and the rapid growth of Field Programmable Gate Array (FPGA) technology, the implementation of ANNs in hardware (known as Hardware Neural Networks, HNN) for complex control problems have become a promising trend. The basic design challenge in such a realization is the effective utilization of FPGA resources and the high-speed restructuring of the ANN circuits. These two factors are having a direct impact on the size, response time and cost of any HNN system. But these two aspects are competing variables, and controlling one factor may result in the violation of the other. In this paper, a simplified optimization technique known as Dynamic Analytic Regulated Configuration (DARC) is proposed. It has been used as a basic design methodology to increase the performance of an ANN architecture by applying a regulated restructuring on FPGA. A single layer feed-forward ANN system has been considered for this work. A brief explanation has been given about the workflow, the DARC structure and the design challenges. A comparison is provided between the static and dynamic restructuring outcomes. The result shows that optimizing both the above constraints is not effective for larger systems at present due to the design limitations and it can be an effective approach for small-scale implementation.