Analog and Mixed-Signal Circuits in Nanoscale CMOS

Table of Contents

1. Frontmatter

2. Radio Front-Ends and Clock References

   1. Frontmatter

   2. High-Performance SAW-Less TDD/FDD RF Front-Ends

      Gengzhen Qi, Pui-In Mak, Rui P. Martins

      Abstract

      In order to develop multiband cellular radios at low cost, the rekindled on-chip N-path switched-capacitor filter is a promising replacement of the off-chip SAW (surface acoustic wave) filters, due to its property of high-Q filtering over a wide RF (radiofrequency) range. This chapter discusses the design of two SAW-less RF front-ends for TDD (time-division duplexing) and FDD (frequency division duplexing). The first is an area-efficient SAW-less wireless transceiver for multiband TDD that utilizes an N-path switched-capacitor gain loop. Fabricated in 65-nm CMOS, the transmitter mode reaches a −1-dBm output power with a −40-dBc ACLR_EUTRA1 at 1.88 GHz and a −154.5-dBc/Hz OB noise at 80-MHz offset; the receiver mode reaches 3.2-dB NF and +8-dBm OB-IIP₃. The second is a fully integrated multiband FDD SAW-less transmitter for 5G-NR in 28-nm CMOS. It features a bandwidth-extended N-path filter modulator to enable both wide bandwidth and high-Q bandpass filtering, also including an isolated baseband (BB) input network and a transimpedance amplifier-based power amplifier driver. The transmitter manifests a 20-MHz passband bandwidth and a low OB noise (≤ −157.5 dBc/Hz) between 1.4 and 2.7 GHz. Under 3-dBm output power, it exhibits high efficiency (2.8–3.6%) and linearity (ACLR₁ <44 dBc and EVM <2%). This chapter presents both designs in detail.

   3. Power-Efficient RF and mm-Wave VCOs/PLL

      Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak, Rui P. Martins

      Abstract

      Almost every electronic system demands a clock signal with high spectral purity. Wireless or wireline systems typically rely on two approaches to enhance the data rate: (1) employing a denser modulation scheme and (2) increasing the operating frequency to secure a large bandwidth. Both approaches impose stringent requirements on the phase noise or jitter of the clock signal. Also, the clock generator needs to be power-efficient in order to improve the battery life of a mobile terminal or save energy dissipation in the data center. This chapter elaborates VCO (voltage-controlled oscillator) and PLL (phase-locked loop) designs, two critical components of a clock generator. The first and third designs demonstrate how the harmonic shaping techniques help to improve the phase noise of the RF and mm-wave VCOs. The second presents an inductive mode-switching technique that can increase the frequency tuning range of the mm-wave VCO without compromising the phase noise. The fourth work is a 25.5–29.9 GHz subsampling (SS) PLL utilizing a master-slave isolated subsampling phase detector to simultaneously obtain low jitter and low reference spur. We verified all four designs with silicon results in 65 nm CMOS (complementary metal-oxide semiconductor).

   4. Ultra-Low-Voltage Clock References

      Ka-Meng Lei, Pui-In Mak, Rui P. Martins

      Abstract

      Clock references are indispensable circuit modules. The Internet of Things (IoT) devices, in particular, usually require a reference with high spectral purity for the phase-locked loop to generate the carrier signal and a low-power always-on reference to serve as the timer. This chapter discusses the design of two clock references operating at ultra-low supply voltage (<0.5 V) for energy-harvesting Internet-of-Things sensor nodes. The first is a sub-0.5 V 16/24 MHz crystal oscillator with a fast startup feature to accommodate the periodic duty-cycling scheme of the Internet-of-Things device. We prototyped the design in 65 nm CMOS (complementary metal-oxide semiconductor). The second is a 0.35 V 2.1 MHz fully integrated relaxation oscillator implemented in 28 nm CMOS. It features an asymmetric swing-boosted RC (resistor-capacitor) network and a dual-path comparator to surmount the challenges of sub-0.5 V operation while achieving temperature resilience. This chapter elaborates both designs in detail.

3. Data Converters

   1. Frontmatter

   2. Low-Power Nyquist ADCs

      Minglei Zhang, Chi-Hang Chan, Yan Zhu, Rui P. Martins

      Abstract

      Analog-to-digital converters (ADCs) bridge the analog and digital worlds, which often confines the system’s performance. In portable or Internet of Things devices, the power budget is extremely tight, calling for low-power ADCs and sometimes even low supply voltage. While with a more complex modulation scheme and crowded spectrum utilization, a large dynamic range is still essential, motivating innovation in circuit, calibration, and architecture levels in the ADC designs. This chapter discusses four Nyquist ADC designs with outstanding energy efficiency. The first is a single-channel 12b 1GS/s ADC with a three-stage pipeline SAR architecture. We introduce next a SAR-TDC hybrid architecture, realizing 20 MS/s with 13b resolution. The third work is a pure pipeline ADC with a new timing arrangement, enabling a single-channel 3.3 GS/s 6b design. The last design is a time-interleaved 8b 10 GS/s TDC-based ADC. This chapter sets forth all the detailed design considerations of the four circuits.

   3. High-Performance Oversampling ADCs

      Chi-Hang Chan, Yan Zhu, Liang Qi, Sai Weng Sin, Maurits Ortmanns, Rui P. Martins

      Abstract

      Modern wireless communications dictate wideband high-resolution ADCs (analog-to-digital converters) with excellent power efficiency. In such context, delta-sigma modulators achieve the goal by utilizing the oversampling property in suppressing the in-band quantization noise. This chapter outlines examples of various oversampling ADCs that reached state-of-the-art performance with excellent power efficiency. The first and second examples are the continuous-time implementation of delta-sigma modulators with the inherent anti-aliasing property, covering a wide bandwidth (BW) of 50–100 MHz. They employ multibit quantization and DAC (digital-to-analog converter) feedback for wide dynamic range, with specific emphasis on the ELD (excess loop delay) compensation, while the third and fourth designs are discrete-time examples based on the modification of the Nyquist Pipeline SAR converter, transforming themselves into the corresponding oversampling counterparts. We utilized dynamic amplifiers in the residue amplifier of the pipeline SAR to obtain excellent power efficiencies. This chapter offers all the detailed design considerations.

4. Energy Harvesters and Power Converters

   1. Frontmatter

   2. Integrated Energy Harvesting Interfaces

      Man-Kay Law, Yang Jiang, Pui-In Mak, Rui P. Martins

      Abstract

      Exploiting renewable energy sources is essential to ensure perpetual system operation of Internet of Things (IoT) devices. With the ever growing demands for higher level of integration and functionality, highly compact energy harvesting interfaces for efficient energy conversion are becoming indispensable. This chapter discusses high-performance integrated switched-capacitor energy harvesting interfaces for miniaturized IoT systems. In terms of the AC-type energy harvesting, we introduce the flipping capacitor rectifier (FCR) and the split-phase flipping capacitor rectifier (SPFCR) to achieve effective voltage inversion for vibration energy harvesting, obtaining a high energy extraction efficiency without using bulky high-Q off-chip inductors. For the DC-type energy harvesting, we exploit the algebraic series-parallel (ASP) topology to reduce both the intrinsic power stage conduction and parasitic losses, while enabling high-efficiency reconfigurable voltage conversion. We demonstrated all the design approaches with silicon-validated results.

   3. Fully Integrated Switched-Capacitor Power Converters

      Junmin Jiang, Yan Lu, Wing-Hung Ki, Rui P. Martins

      Abstract

      Since both switches and capacitors shrink with advanced integrated circuit processes, fully integrated switched-capacitor (SC) power converters become a popular solution for on-chip point-of-load power delivery. This chapter covers the topology design, multiphase and multistate operations, loss analyses, and efficiency optimization considerations for a better fully integrated SC power converter design. Then, we will introduce two SC power converter design examples. The first is a 100+ multiphase ring-shaped fully integrated SC converter that surrounds the load placed in the middle, thus providing high-quality power supply through any edges of the chip. In addition, the first work significantly extended the loop bandwidth with an innovative pseudo-continuous control loop design. The second work is a dual symmetrical SC converter with dynamic power cell allocation, such that the two outputs can efficiently share the power converter cells with higher system efficiency and smaller chip area. This chapter included all design considerations.

   4. Hybrid Architectures and Controllers for Low-Dropout Regulators

      Xiangyu Mao, Mo Huang, Yan Lu, Rui P. Martins

      Abstract

      Fine-grained supply voltage management is highly favorable for high system power efficiency of a system-on-a-chip (SoC) or multicore microprocessors. Fully integrated low-dropout regulators (LDOs) can provide a compact and cost-effective solution to supply the multiple divided and adaptive voltage domains. Meanwhile, they enable a fast dynamic voltage and frequency scaling (DVFS) for digital systems. A conventional analog LDO (A-LDO) may not fit well in such high-current applications, due to its relatively low-frequency pole at the gate of the power transistor, and the performance degradation in a low-input voltage case. Instead, digital LDO (D-LDO), switching LDO (S-LDO), and hybrid architectures are more suitable for the digital loads. This chapter first discusses the classic LDO control methods and power stage selection considerations. Then, we detail the design techniques of the analog-assisted digital LDO, hybrid controlled LDO, and the ampere-level switching LDO, in an advanced nanoscale CMOS (complementary metal-oxide semiconductor) process.

5. Backmatter