Analog Circuit Design

Aggressive device scaling down to the nano-meter range offers IC designers both opportunities and challenges. Digital designers benefit greatly from the system flexibility and affordability, but analog/RF designers are struggling with flawed devices. Since scaled devices are faster and smaller, the incentive to use such strengths advantageously has prompted many efforts to overcome analog imperfection by digital means. Designers are introducing more DSP functionality to enhance the performance of analog/RF systems. More intelligence is being built into analog/RF designs as in linear PA, RF receiver front-end, ADC/DAC, digital PLL, etc. Such pervasive design techniques with digital assisting will prevail in the future SOC design. After a brief overview of the trend, examples of the LMS-based calibration algorithm applied to the pipeline and CT cascaded ΔΣ modulator are discussed.

In this paper an overview of state of the art techniques to measure and correct non-idealities in a pipelined ADC is given. The paper discusses the motivations for digital calibration, and subsequently details state of the art calibration approaches. System tradeoffs of commonly used calibration techniques are analyzed. A discussion of how digital calibration can be used to enable the next generation of very low power ‘smart-ADCs’ is also given.

High-resolution wide-bandwidth ADCs in nm-CMOS are key enablers in increasing the level of digitization and integration in cellular base station receivers. This paper discusses smart techniques to overcome the limitations of low supply voltage and low intrinsic device gain. A 14 b 100 MS/s ADC in 90 nm CMOS is described demonstrating that good power efficiency can be achieved in nm-CMOS with a low supply voltage.

The idea of time-interleaved ADCs (TI-ADCs) is old, but it took more than 25 years until the requirements on converters and the possibility of advanced digital post correction made this architecture attractive. We investigate time-interleaved ADCs with a focus on the involved signal processing. By establishing a discrete-time model of a TI-ADC, we explicitly show that a TI-ADC with mismatches is a time-varying system producing spurious images. This view will help to understand the principles of digital calibration of linear mismatches in TI-ADCs. Currently, time offset mismatches are investigated most extensively. Therefore, we will primarily discuss digital calibration of time offset mismatches, but will generalize the results to frequency response mismatches whenever possible.

This paper classifies correction methods for current-steering Digital-to-Analog Converters (DACs), with an emphasis on self-calibration. Based on this classification, missing methods are identified. Three new DAC correction methods are proposed that can fill in these gaps: high-level mapping, suppression of HD, and calibration of binary currents. All three of them are based on parallel sub-DACs. The paper also proposes to further exploit the advantages of using such parallel sub-DACs to achieve flexibility. Two test-chip implementations in 250 and 180 nm CMOS validate the proposed concepts.

The current-steering D/A-converter is the workhorse for the synthesis of high-resolution, wide-bandwidth analog signals, e.g. in the transmitter section of digital transceivers. Highly integrated systems require the implementation of such circuits in a nanometer CMOS technology together with analog and digital signal processing functions. Multi-mode operation additionally complicates the design task, since it is desired to minimize the circuit overhead in terms of silicon area and power consumption. “Smart” data converters make use of auxiliary analog and digital circuitry to enhance the linearity and to eventually tailor the converter architecture to the specific operating mode.

Doubly resistively terminated LC filters are optimal from an element sensitivity point of view and are therefore used as reference filter for high-performance active filters. The later inherits the sensitivity properties of the LC filter. Hence it is important to design the reference filter to have minimal element sensitivity. In this paper, we first review the mechanism for the low sensitivity and give an upper bound on the deviation in the passband attenuation. Next we compare classical lowpass approximations with respect to their influence on the sensitivity and propose the use of diminishing ripple in the passband to further reduce the sensitivity. Finally, we propose a design strategy for doubly resistively terminated LC filters with low sensitivity.

High performance continuous time filters based on operational transconductance amplifiers (OTAs) are discussed. Several OTA linearization techniques are reviewed, and a design example is provided with measurement results. To address the problem of inaccuracies in continuous time filters, two direct tuning techniques are presented with applications to ultra-wideband (UWB) receivers and bandpass sigma-delta modulators.

Continuous-time (CT) analog filters based on source-follower circuits and on a local positive feedback to synthesize negative resistances and complex poles are here proposed. The intrinsic source-follower feedback allows these filters to perform large linearity for smaller V_OV( = V_GS − V_TH). This is exactly the opposite of the other CT filters where linearity performance improves with V_OV and with the current consumption increasing. Two circuit implementations will be shown. The first filter uses a cascade topologies to synthesize a fourth-order lowpass filter. In a 0. 18 μm CMOS at 1.8-V supply, it achieves a 17.5 dBm IIP3 and a − 40 dB HD3 for a 600-mV_pp–diff input signal amplitude. A 24 μV_rms noise gives a DR = 79 dB, with 2.25 mA current consumption. The second filter exploits a ladder topology to synthesize a sixth order low-pass filter frequency response. In a 0. 13 μm CMOS technology with V_DD = 1. 2 V, the cut-off frequency is 280 MHz while the DC gain is 0 dB. An 11 dBm IIP3 has been measured. The output noise is about − 140 dBm at 3 MHz.

This paper presents a wideband reconfigurable active-RC filter designed for home networking applications. The reconfigurable filter is embedded in an analog front-end chip (AFE) for HomePNA and PLC applications. The AFE, implemented in a 0. 13 μm CMOS technology, offers a high-performance analog receive and transmit path required to deliver the multi-100 Mbps targeted system level performance. With a measured SNR of 58 dB and a linearity of 95 dB, and a noise level of \(3\,\mathrm{nV}/\!\surd \mathrm{Hz}\), the AFE is well suited to accommodate high data rate modulation schemes. The integrated third order filter has a programmable low-pass filter from 14–60 MHz with 1 MHz increments. A digital control loop compensated for PVT variations with 1 MHz accuracy. The AFE runs from 3.3/1.2 V supplies and consumes 152/221 mA for a full scale differential output current setting of 80 mA ptp.

Instantaneous companding offers several advantages over conventional AGC techniques to deal with the high Peak-to-Average Power Ratio (PAPR) and high dynamic range (DR) associated with wireless signals in a low-voltage environment. The practical on-chip implementation of such internally non-linear systems, however, poses several challenges that arise due to process non-idealities. This paper presents the design and on-chip implementation of a companding baseband channel-select filter for WLAN 802.11a/g receivers. The filter is implemented as a fifth order Chebyshev type Switched Capacitor (SC) filter with a cut-off frequency of 10 MHz and with companding by a factor of four in IBM’s 1.2 V, 130 nm CMOS technology. It achieves an almost flat Signal-to-Distortion Ratio (SDR) of around 50 dB when companding takes place in the higher end of the DR of the input signal. No AGC is required in the baseband in front of or within the filter and a reduction in power consumption by a factor of 3.3 is achieved with respect to the conventional filter designed for the same DR.

This paper presents a particular type of GHz frequencies high-quality Silicon integrated filters using BAW resonators. By enhancing BAW resonators with active Silicon “intelligence”, process and temperature variations of such high quality factor band-pass filters may be compensated. After presenting some theoretical aspects, this paper presents the design of a frequency tunable BAW filter together with the implementation of its tuning circuitry. System-in-Package (SiP) co-integration aspects between Silicon and BAW technologies are also presented.

Traditionally, multimode transmitters are approached from a linear circuit approach, and then significant work follows to improve their abysmal initial energy efficiency. Here we consider the reverse procedure, where the starting point is the circuit with greatest energy efficiency – a switch – surrounded by system architectures which result in exactly the same output signals. This latter approach necessarily leads to polar signal processing and polar modulation techniques.

This text gives an overview of critical technology challenges for high efficiency power amplifiers used in future mobile broadband systems. Implementation aspects of efficient wideband multi-band transmitters are discussed. Simulations of and design implications for a multi-band 1.8–2.7 GHz high efficiency power amplifier using GaN transistors are presented. Finally possible transmitter architectures with potential of meeting ambitious efficiency, flexibility and frequency range goals are briefly analyzed.

This paper both describes a multi-mode modulator for cellular 2.5, 3 and 4G applications and a multi-mode transmitter for connectivity standards like Bluetooth (BT), Zigbee and WLAN. Both multi-mode transmitters are implemented in deep submicron CMOS technology and demonstrate the use of digital techniques and innovative analogue circuit topologies for obtaining high efficiency and excellent performance. The two multi-mode transmitters have different architectures as their target applications impose different performance requirements.

Several PA efficiency enhancement techniques, tailored towards CMOS implementation, are discussed. It will be shown how the combination of reconfigurable PA circuitry, together with the fast processing power of CMOS, can result in novel TX and PA architectures that achieve a higher efficiency when amplifying amplitude modulated signals

This paper presents an all-digital approach to the generation of the modulated radio-frequency carrier and its application to a multimode transmitter in today’s communication systems and draws a possible picture of tomorrow’s systems. We will first analyze how digital transmitters will progressively replace their analog counterparts and what are the main issues associated with this trend. The combination of Δ​Σ modulation and digital mixing is proposed as an innovative approach enabling multimode operation of transmitters with low power consumption and chip area, easy configurability, and good performance. A 90 nm CMOS chip has been designed to demonstrate the feasibility of the concept and its potential in multimode transmitter architectures. Techniques such as redundant arithmetic and non-exact quantization are used in the high-speed Δ​Σ modulator implementation. Furthermore, approaches to antenna filtering using BAW filters and reconfigurable semi-digital RF FIR filters will be introduced. Finally, a review of recent outstanding transmitter designs will allow a comparison between the presented approach and architectures based on digital-to-RF conversion.

With the introduction of new cellular phone standards with increased modulation complexity and signal bandwidth, the design of efficient transmitters will be a major challenge. With this in mind a number of switched mode transmitter architectures are described, both polar and Cartesian ones. The most promising candidates use a combination of supply voltage modulation and other techniques, such as radio frequency pulse width modulation (RF PWM) or polar delta sigma modulation. This takes advantage of the high efficiency of supply voltage modulation combined with the high speed of the other techniques. Since the architectures are polar, however, significant bandwidth expansion occurs, increasing the requirements on the baseband circuits. Also for Cartesian architectures supply voltage modulation can be used to increase the efficiency, for instance in a double LINC architecture.