This chapter focuses on circuit-level techniques, completing the analysis of radiation hardening by design (RHBD) methods across various design abstraction levels. Here, we evaluate the charge sharing effect, considering its dependence on cell placement and logic synthesis. Subsequently, an optimization methodology is proposed to enhance overall circuit hardness through signal probability–based pin swapping.
6.1 Reliability-Driven Synthesis
The synthesis process is an essential stage in very-large-scale integration (VLSI) system design using integrated circuits (ICs) as it determines critical performance characteristics of the application, such as timing, power consumption, and area efficiency. However, this process also significantly impacts the final circuit’s reliability, especially when considering radiation effects such as soft errors. Consequently, various approaches can be integrated into the synthesis flow to enhance this aspect. This chapter analyzes and proposes mitigation strategies as a novel radiation hardening by design (RHBD) approach applicable during both logical and physical synthesis in VLSI systems, offering significant improvements in circuit robustness under radiation effects.
Electronic circuit development for space and aviation can employ various design methodologies, ranging from field programmable gate arrays (FPGAs) to full-custom or cell-based application-specific integrated circuits (ASICs). While FPGA-based designs offer fast prototyping, they often sacrifice area and performance compared to full-custom designs [1, 2]. On the other hand, ASICs strike the best balance between performance, power consumption, and circuit area. The standard cell methodology is a primary approach in ASIC design, wherein thousands of predesigned and characterized logic gates, known as “standard cell logic gates,” are utilized for designing complex VLSI circuits. The synthesis of a Boolean function can lead to varying combinations of logic cells, affecting the number of transistors and layout design, which directly influences the radiation robustness of the circuit. Once vulnerable nodes are identified within a circuit, hardening techniques such as gate sizing or hardware redundancy can be employed to enhance overall reliability [3, 4].
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There is a growing trend within the research community to incorporate radiation hardening techniques early in the VLSI circuit design flow [5‐10]. The proposed predictive single-event transient (SET) characterization methodology (discussed in Sect. 3.4) can be integrated into the logic synthesis of a cell-based circuit design, as illustrated in Fig. 6.1. Starting from a register transfer level (RTL) description, logic synthesis translates a function into a netlist description of logic gates using a designated standard cell library. The logic synthesis of a VLSI circuit comprises three main processes [11]:
Fig. 6.1
Integration of SET characterization of standard cell libraries for a reliability-driven logic synthesis
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1.
Gate-level optimization independent of technology: Boolean equations described in the RTL are optimized to minimize size and the number of literals.
2.
Technology mapping: Transforms each logic function into a logic gate (NAND, NOR, AND, OR, etc.) from the provided cell library.
3.
Technology-dependent gate-level optimization: Optimizations on the gate netlist are conducted to minimize delay in critical paths, power consumption, and area usage.
RTL, or register transfer level, serves as an abstraction for digital circuits, emphasizing the movement of data between registers. It offers a middle ground between high-level concepts and low-level transistor details.
The gate netlist, a logic-level representation of the circuit, includes gate instances from the standard cell library and their corresponding port connectivity. Consequently, the logic synthesis has a major impact on the resulting gate netlist and thus on the single-event effect (SEE) immunity of the final circuit design. During technology mapping, the technology-independent circuit is broken down into fundamental primitive logic cells (e.g., INV, NAND, or NOR gates). Subsequently, after the decomposition, a pattern-matching process identifies structural and functional patterns to be utilized in the covering process. Here, the optimal patterns are chosen based on a cost function considering factors such as delay, area, and power consumption. Hence, by evaluating the SET immunity of basic logic cells and their combinations, it becomes feasible to develop a reliability-driven cost function and integrate it into the technology mapping process.
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The physical design process translates the synthesized gate netlist into the geometric representations used for manufacturing, known as the circuit layout. This stage involves placing each logic cell layout and routing its connections to minimize wire length and optimize power/performance. However, the study conducted by Entrena et al. [3] proposed a cell placement approach focused on reducing charge sharing effects, thereby improving the single-event rate (SER) performance of the circuit.
Similarly, by leveraging the SET characterization methodology on a cell library, a set of SET-aware logic transformations can be integrated into the logic synthesis stage to enhance the SET immunity of the final synthesized gate netlist. Figure 6.2 illustrates the SET cross section of the six most commonly used standard cell logic gates for two-particle linear energy transfer (LET) values.
Fig. 6.2
SET cross section for eight standard cell gates from 45 nm NanGate [12], for LET equal to 78.23 and 9.94 \(\mbox{MeV.cm}^2/\mbox{mg}\)
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The AND-OR inverter (AOI) and the OR-AND inverter (OAI) gates implement a larger logic function, resulting in a larger layout area. Consequently, a higher SET cross section is observed when compared with the primitive logic cells. Based on this information, a SET-aware technology mapping could be adopted by assigning a reliability cost to each logic gate. The weight or cost of each gate can be calculated based on the radiation requirements of the mission and the SET cross section or the estimated in-orbit SET rate. This strategy would enable the selection of gate types during technology mapping with consideration for their impact on circuit reliability in radiation-prone environments.
6.1.1 Multiple \(V_{th}\) Cells and Voltage Scaling
A primary objective of logic synthesis is to minimize delay in critical paths. This is achieved by selecting cells with lower propagation times, often facilitated by the adoption of multiple threshold voltage (\(V_{th}\)) circuits [13]. Devices with lower \(V_{th}\) values exhibit faster switching times, thereby accelerating circuit operation. However, this comes at the expense of increased static power consumption due to higher leakage currents. Conversely, employing high \(V_{th}\) devices reduces leakage currents but may lead to performance degradation. Consequently, multiple \(V_{th}\) cells are commonly utilized to optimize the gate netlist with respect to both delay and power consumption [14].
An efficient SET characterization methodology can also address the assignment of multiple \(V_{th}\) values. Figure 6.3 illustrates the characterization of standard cells using high-performance (HP) process technology, featuring low \(V_{th}\) devices, and low-power (LP) process technology, featuring high \(V_{th}\) devices. As expected, circuits based on LP technology exhibit a higher overall cross section. This aligns with prior research demonstrating that increased threshold voltage degrades driving strength [15‐17]. Notably, NAND gates are the most sensitive to variations in \(V_{th}\), with cross-section increase of 95%. Despite their higher cross sections, complex logic gates such as AOI21 and OAI21 demonstrate relatively low increases.
Fig. 6.3
Impact of different threshold voltage devices: High-Performance (HP) vs. Low-Power (LP) devices
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Besides impacting the SET cross section of logic gates, the different \(V_{th}\) devices can also impact the masking effects and the SEU cross section of memory cells.
While dynamic voltage scaling is another technique for low-power systems [18], reducing supply voltage increases delay and radiation sensitivity [19, 20]. In Fig. 6.4, the SET cross section of each gate is estimated while considering supply voltage scaling from 1 V down to 0.4 V, approaching the near-threshold regime.
Fig. 6.4
Estimation of the dynamic voltage scaling impact on the SET cross section of the standard cells
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Decreasing the supply voltage directly diminishes the critical charge necessary to observe an SEE in the circuit output [19]. Notably, at nominal voltage, NAND gates offer a lower SET cross section compared to NOR gates. However, under voltage scaling to 0.4 V, NOR gates exhibit a lower cross section. This discrepancy stems from the varying impact of drive capability on the transistor networks present in each gate design. Consequently, for low-power systems employing dynamic voltage scaling, logic synthesis should favor NOR gates over NAND gates to enhance radiation hardness.
6.1.2 Technology Mapping
Reliability-aware logic synthesis, incorporating mitigation strategies for soft errors, involves hardening a complex circuit by selectively employing logic gates that minimize SET generation or propagation in the most vulnerable sub-circuits of a complex VLSI design [5]. For example, the radiation robustness of the circuit can be enhanced by selecting the optimal combination of standard cells that facilitates the pulse quenching effect (PQE) induced by inter-cell charge sharing in electrically related combinational circuits [21, 22]. As previously mentioned, technology mapping is responsible for translating Boolean logic functions described in RTL codes into actual physical logic gates available in a cell library.
Consider the buffer gate, a commonly used circuit amplifier in VLSI circuit design, depicted in Fig. 6.5. Unlike the inverter gate, a digital buffer outputs a signal of the same logic state as its input signal. Buffer insertion, also known as repeater insertion, is a well-established technique in VLSI systems to enhance circuit performance in submicron technology [23]. Moreover, with technology scaling, buffer insertion becomes increasingly important due to the rise in wire delays [24]. Consequently, it is crucial to assess the radiation robustness of buffer gates provided by cell libraries.
Fig. 6.5
Transistor schematics, truth table, and symbol of a digital CMOS buffer gate
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From the RTL description of a circuit, the implementation of the buffer Boolean function can be synthesized into either a single buffer (BUF) gate, typically available in the cell library, or two interconnected inverter (INV) gates. Although both implementations realize the same logic function, different radiation sensitivities may be expected due to their distinct layout implementations provided by standard cell design and the cell placement obtained in physical synthesis. Similar differences can be anticipated when implementing the logic functions OR and AND. To analyze which gate combination offers the best SET robustness, in the work developed at [22], the BUF, AND, and OR gates were evaluated under heavy ions and compared with INV, NAND, and NOR gates coupled with an inverter in their output.
Three distinct horizontal cell placement configurations were analyzed to assess the effectiveness of charge sharing and its consequent pulse quenching effect. Vertical placements (electrically connected cells in separate rows) were excluded from this study as prior research has shown that they eliminate the pulse quenching effect due to increased nodal separation and the presence of well contacts that significantly reduce charge sharing efficiency [25]. All cells were minimum-sized drive strength (X1) designs from the bulk 45nm technology cell library. The SET cross section (\(\sigma _{SET}\)) for the BUF gate and the connected inverters (with the second inverter placed four minimum cell widths, i.e., 1520 nm from the output of the first inverter) are presented in Fig. 6.6. Clearly, the BUF design has a lower overall SET cross section. This design places the two sensitive nodes closer together compared to the INV \(+\) INV setup, enhancing the charge sharing effect. Due to the electrical relationship between these sensitive nodes (inverting stage), pulse quenching effect (PQE) is observed, reducing sensitivity to radiation-induced transient pulses.
Fig. 6.6
SET cross-section curve for the BUF gate and the INV \(+\) INV\({ }_{3}\) circuit. The inverter gate INV\({ }_{3}\) is placed 1520 nm from the output of the first inverter
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Moreover, upon examining the layout design of the buffer gate, it becomes apparent that the first-stage inverter has smaller transistor sizing than the second-stage inverter, as depicted in Fig. 6.7. By reducing the transistor sizing of the first stage, the SET pulse propagated to the second stage is shorter than in the INV+INV design. As the drain collection area in the second inverter remains unchanged in both designs, in the buffer gate, a shorter transient pulse is induced in the first inverter stage while maintaining the same PQE effectiveness in the second-stage inverter, demonstrating its superior robustness.
Fig. 6.7
Comparison of the collecting drain area of the sensitive electrodes in the first and second stage inverters from the BUF gate and INV \(+\) INV design. In the case of the INV \(+\) INV\({ }_{3}\) circuit, INV\({ }_{3}\) is placed 1520 nm from the output of the first inverter, increasing the distance between the collecting drain areas
×
While the optimal implementation for the buffer boolean function has been shown to be the BUF gate from the studied cell library, for the OR boolean function, the NOR \(+\) INV circuit might present a lower SET cross section [22]. Despite the reduced transistor sizing in the internal NOR circuit within the OR gate layout, the NOR+INV circuit continues to offer a lower \(\sigma _{SET}\), highlighting its robustness. Unlike the inverter gate, NOR and NAND gates include transistors in series, potentially degrading the recovering current of the circuit. Moreover, while the NAND \(+\) INV circuits do not exhibit a lower \(\sigma _{SET}\) compared to the NOR \(+\) INV circuits, the NMOS device in the NAND gate’s output inverter dominates the pulse quenching effect when the input vector is (1, 1), resulting in a different response compared to the NOR \(+\) INV schemes. These findings highlight the importance of evaluating different logic gate combinations during synthesis to achieve optimal radiation hardness for reliable VLSI circuits.
In addition to the basic primitive logic gates (INV, NAND, NOR, etc.), standard cell libraries also offer complex logic gates such as the AND-OR inverter (AOI) and OR-AND inverter (OAI) cells. The usage of such standard cells reduces the number of transistors in the circuit, resulting in denser layouts, decreased power consumption, and smaller area requirements [26]. For instance, the Boolean logic function represented in Eq. 6.1 can be realized using basic logic standard cells like NOR and AND gates, or directly employing the complex gate AOI [27].
Implementing Equation 6.1 with the AOI21 gate reduces the transistor count by 40% compared to using an AND gate coupled with a NOR gate. Similarly, the OAI21 gate achieves the same reduction for the complement of Eq. 6.1. Although the power consumption of complex logic gates is reduced, predicting their radiation sensitivity is challenging. The radiation performance of complex logic gates AOI21 and OAI21 is compared with their corresponding implementations using only basic logic gates such as AND, OR, NAND, and NOR.
The SET cross-section curves considering only P-hit interactions, is shown in Fig. 6.8. In this scenario, all PMOS devices are turned off by setting the input signals to (1, 1, 1). It clearly shows that the implementation containing the basic logic cells AND \(+\) NOR provides a lower SET cross section than the AOI21 for the entire LET range. Both circuits present the same threshold LET, whereas there is a SET cross-section difference of approximately a factor of 2. The charge sharing effect and more importantly the logical masking between the AND gate and NOR gate are responsible for this reduced number of observed SET in the output of the AND \(+\) NOR implementation [27].
Fig. 6.8
SET cross-section curve of P-hit interactions for the complex logic AOI21 gate and AND \(+\) NOR implementation
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Any SET induced at the AND gate will be filtered by the logic of the NOR gate as observed in the truth table shown in Fig. 6.9. The output of the NOR gate will remain at logic zero as long as the secondary input remains at logic one. This masking effect is not observed for the N-hit configuration. However, by analyzing the structure of the combinational logic and the electrical simulation results, the SETs observed for the AND gate are logically masked by the NOR gate, thus reducing the overall drain sensitive area to the PMOS devices issued in the NOR gate [27].
Fig. 6.9
Logical masking effect for the P-hit configuration in the combinational logic circuit AND \(+\) NOR. There is no logical masking when both inputs are set to logic zero
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Fig. 6.10 presents the comparison between the SET cross section of the AND \(+\) NOR implementation and the standalone NOR gate. It can be observed that logical masking is effective by reducing the sensitivity of the circuit close to the sensitivity of the standalone NOR gate.
Fig. 6.10
Comparison of SET cross-section curve of the AND \(+\) NOR implementation and the standalone NOR gate
×
Considering only the N-hit interactions, the SET cross sections are approximately the same for high LET ions due to very similar N-hit sensitive areas. Further, there is no contribution of logical masking effect for the input signals considered. As shown in the truth table of the NOR gate in Fig. 6.9, its output is determined whenever one of its input is at logic one. Then, as originally both inputs are set to logic zero, whenever a generated SET at the AND gate propagates to the NOR gate, it will be able to propagate to its output in the case of not being electrically attenuated. In this case, only the electrical masking effect takes place.
6.2 Pin Assignment
The SET characterization of logic gates presents an input dependence due to the varying interplay between sensitive collecting drain areas and restoring current, as previously discussed in Chap. 5. While signal switching activity has long been used to estimate power consumption in VLSI circuit design, it can also support reliability analysis, as demonstrated in [28‐30]. Generally, the SET cross section of a digital circuit is given for a specific input signal combination or for the arithmetic mean between the cross section obtained for each input signal combination of the truth table, i.e., the same probability to each input combination is considered. However, the predictive SET characterization (described in Chap. 3) can incorporate signal probability information from a given system application to estimate a more realistic cross section. By considering signal probabilities, more application-efficient mitigation transformations can be proposed in circuit synthesis (Fig. 6.1).
Signal switching activity in VLSI systems serves multiple purposes, including estimating power consumption and performing timing analysis [31‐33]. Given the sensitivity of circuits to SET, which is influenced by layout and operational factors such as input signals and internal states, signal probability can be leveraged to enhance circuit reliability [34]. Signal probability-based reliability analysis (SPRA) is an effective tool for analyzing the reliability of VLSI circuits at the gate level [29, 35, 36]. Here, reliability refers to the confidence level that the output will be functionally correct given a fault probability. Initially, SPRA methods focused on physical defects due to wear-out mechanisms or process variability [35]. However, with increasing interest in reducing soft error rates, research has expanded to analyze SET [7, 9, 29, 36]. For instance, [9] proposed a cell placement strategy based on defining bad and good pairs of logic gates to minimize circuit error rates. Similarly, [7] suggested a cell placement approach considering signal probability and its impact on the pulse quenching effect.
In this section, we will discuss how a reliability-driven pin assignment optimization based on the input dependence of SET sensitivity of logic gates can be used to improve the robustness of a given complex digital circuit.
6.2.1 Optimization of Pin Assignment for Single-Event Transients
Pin assignment in logic synthesis enhances power and performance metrics in VLSI circuit design by exploiting the functional equivalence of input pins of logic gates [11, 37, 38]. Consider the NAND gate and its truth table in Fig. 6.11. A symmetric input relationship is evident when both input signals are not identical (i.e., A \(\neq \) B): the output signal is determined whenever one of its inputs is in the low logic level, regardless of the input pin (a or b). The interchangeable input combinations are highlighted in Fig. 6.11 (red rectangle). This symmetric input relationship holds true for all two-input basic standard cell gates.
Fig. 6.11
Schematic of the transistor network of a two-input NAND gate and its truth table. The interchangeable input combinations are highlighted by the red rectangle
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As each input pin of a logic gate presents different electrical characteristics depending on the transistor network, power-driven logic synthesis assigns the input signal with lower switching activity to the pin with higher capacitance. Similarly, a timing-driven optimization can apply pin permutation between symmetric input pins such that the late-arriving signal is always connected to the input pin with the lowest intrinsic delay [11]. This process is known as rewiring or pin swapping [37, 38]. Considering that cross section of logic gates is dependent on the input stimuli, a reliability-aware synthesis can be proposed based on the cell symmetric inputs and signal probabilities to improve the vulnerability of the circuit through optimal pin assignment.
The proposed SET-aware pin assignment optimization in a cell-based circuit design flow is illustrated in Fig. 6.12. Beginning with a circuit description in RTL, logic synthesis optimizes each Boolean function and maps it to logic gates available in the standard cell library. The resulting gate netlist, typically optimized for timing, area, and/or power, is then utilized alongside the standard cell library for the SET-aware pin assignment optimization.
Fig. 6.12
SET-aware pin assignment optimization in a cell-based VLSI circuit design flow
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The first step involves the input-based SET characterization, where the symmetric input relationship of each standard cell is identified, and the SET cross section for interchangeable input combinations is calculated. For example, the cross section for input combinations (0, 1) and (1, 0) is determined. Based on the SET characterization results, a set of pin assignment rules is defined. This entails assigning an input pin for each standard cell so that the net with the lowest signal probability is connected, ensuring that the most sensitive interchangeable input combination has the lowest probability of occurrence.
In the second step, considering the switching activity of the primary inputs, the calculation of signal probability can be performed for internal net connections, as depicted in Fig. 6.13. Using the Boolean function of each gate, an equation is derived to calculate the probability of the output signal being at logic value 1, denoted as \(P_{GATE} (output = 1)\). In this study, the Parker-McCluskey method [39] was employed, assuming uncorrelated primary inputs with equal switching activity of 50% (signal probability equals 0.5). Although temporal and spatial correlations are not considered in our analysis, more sophisticated and accurate signal probability estimation methods can be seamlessly integrated into the development flow depicted in Fig. 6.12. Utilizing basic probability theory, the output signal probability equations for the logic gates used in the combinational circuit in Fig. 6.13 are presented in Table 6.1.
Fig. 6.13
Signal probability estimation for a combinational logic circuit. Primary input signal probability is assigned to 0.5
Table 6.1
Signal probability estimation for the INV, NAND, NOR, and XOR gates
aSignal probability is the probability of the signal to be at logic value 1
×
For instance, consider the inverter gate. Given the input probability \(p(a=1)=1\), i.e., the signal is always at logic value 1, considering its Boolean function, the probability of the output signal to be at logic value 1 is 0 (\(P_{INV} (output=1)=0\)). Thus, the signal probability equation for the inverter can be expressed by Eq. 6.2:
For clarity, the probabilities \(P_{GATE} (output=1)\), \(p(a=1)\), and \(p(b=1)\) will be shortened to \(P_{GATE}\), \(p_{A}\), and \(p_{B}\). Following the signal probability calculation step in the Fig. 6.12 is the pin swapping process. In this process, with the pin assignment rules and the signal probabilities, an optimization algorithm can identify which pin should be swapped in order to reduce the occurrence of the interchangeable input combination with the higher SET cross section. After the pin swapping, the standard design flow is performed with the optimized netlist.
In order to obtain important reliability information to be addressed in the optimization process, the SET characterization methodology is aligned to the identification of the input dependence [34, 40]. The sensitivity of each standard cell is extracted from the layout design in the Graphical Design System (GSDII) file. Thus, the Monte Carlo simulation tool, MC-Oracle [41], is used to obtain the SET currents. In order to consider the input signal probabilities, Eq. 6.3 is used. Given n input combinations, the overall gate SET cross-section \(\sigma _{Gate}\) can be estimated from the input SET cross-section \(\sigma _{SET}(i)\) and the input probability \(p(i)\):
The input cross-section \(\sigma _{SET}(i)\) is provided by the SET characterization, while the input probabilities are provided by the signal probability calculation in Fig. 6.13. Then, this equation is used in the Pin Swapping process to evaluate when the input pins assigned from the logic synthesis should be swapped to decrease the gate SET cross section. Similarly, this process can also adopt the soft-error rate estimation for a given mission orbit as shown in [40].
6.2.2 Impact on the SET Cross Section of Standard Cells
Based on the cross section of the interchangeable input combinations, an optimized logic synthesis should prioritize the pin assignment of the lowest signal probability in such a way the most sensitive interchangeable input combination obtains the lowest probability of occurrence [40]. The input SET cross section for NAND, NOR, and XOR gates under particle linear energy transfer (LET) of 5 \(\mbox{MeV.cm}^2/\mbox{mg}\) is shown in Fig. 6.14. It is possible to identify the most sensitive input combinations for each gate. Considering the interchangeable input, i.e., (0, 1) and (1, 0), the NAND gate is the only cell to show the lowest cross section for (1, 0), while the NOR and XOR gates present (0, 1). It implies that, considering low-particle LET, the lowest signal probability should be assigned to the input B for the NAND gate and to the input A for the NOR and XOR gates.
Fig. 6.14
Input SET cross section for the NAND, NOR, and XOR gates under a particle with LET \(=\) 5 \( \mbox{MeV.cm}^2/ \mbox{mg}\)
×
When adopting a three-input logic function such as AOI21 and OAI21, it is not possible to obtain a complete symmetric input relationship as observed for the two-input gates. It is necessary to identify the interchangeable input combinations and also what we denominate as the controllable input pin, i.e., the pin that controls the output of the function and the pin assignment cannot optimize it; otherwise, it will interfere with the correct logic function of the circuit. In [40], this methodology is explained in detail and the results for the AOI21 and OAI21 under an LET of 5 MeV.cm2/mg is shown in Fig. 6.15.
Fig. 6.15
Input SET cross section for the AOI21 and OAI21 gates under a particle with LET \(=\) 5 \( \mbox{MeV.cm}^2/ \mbox{mg}\)
×
By applying Eq. 6.3, we can obtain the overall gate SET cross-section \(\sigma _{Gate}\) for a given input scenario. Figure 6.16 provides the gate SET cross-section \(\sigma _{Gate}\) curves for the NOR gate considering two signal probability scenarios [a: 0.9, b: 0.1] and [a: 0.1, b: 0.9]. For high LET, a slight reduction is observed in the cross section when the lowest signal probability is assigned to the input pin b as it reduces the impact from the input combination (0, 1). However, for low LET, the cross section can be drastically reduced if the lowest signal probability is assigned to the input pin a, instead. With the reduction of the particle LET, the impact on the overall gate sensitivity is dominated by the input combination (1, 0), being comparable to the worst-case input scenario for this logic gate, the input (0, 0). For instance, a SET cross-section reduction of solely 9% can be obtained for the pin assignment [a: 0.9, b: 0.1] when the LET is 78.23 \(\mbox{MeV.cm}^2/\mbox{mg}\), while a reduction up to 86% is expected for [a: 0.1, b: 0.9] under 2.53 \(\mbox{MeV.cm}^2/\mbox{mg}\).
Fig. 6.16
SET cross-section curves for the two-input NOR gate considering two signal probability scenarios: Lowest signal probability assigned to input pin a [a:0.1, b:0.9]; lowest signal probability assigned to input pin b [a:0.9, b:0.1]
×
To verify this impact within a mission environment, the gate reliability can be examined in terms of in-orbit SET rates. Figures 6.17 and 6.18 present the in-orbit SET rates calculated using the OMERE tool [42], based on NOR gate SET cross-section curves shown in Fig. 6.16. The standard method for calculating the SEE rate, as specified by the European Cooperation for Space Standardization (ECSS), employs the integral rectangular parallelepiped (IRPP) method [43]. The SEE rate is derived through the convolution of the cross-section data with the particle flux in the mission orbit.
Fig. 6.17
In-orbit SET rate calculated based on the proposed SET characterization considering the International Space Station (ISS) orbit, 400 km, 51.64\({ }^{\circ }\)
Fig. 6.18
In-orbit SET rate calculated based on the proposed SET characterization considering a Geostationary Orbit (GEO), 35,784 km
×
×
In this study, the SET rates were computed for both a geostationary orbit (GEO) and a low-Earth orbit (LEO) International Space Station (ISS) orbit. Employing a fixed shielding of 1 \(\mbox{g/cm}^2\), the international standard ISO 15390 model is utilized for the galactic cosmic rays (GCR) [44], while the NASA AP8MIN trapped radiation model is adopted for the trapped proton flux under solar minimum conditions [45]. The results are segmented into heavy-ion, proton, and total rates (combining heavy-ion and proton rates).
The significant impact of the pin assignment is evident in heavy-ion rates, showcasing a reduction of approximately 83% and 92% on the SET rate for the GEO and ISS orbits, respectively. However, in the ISS orbit, protons are anticipated to dominate the SEE rate, as depicted in Fig. 6.17. By accounting for the contributions of heavy ions and protons to the SET rate of the two-input NOR gate, a SET-aware pin assignment could yield a reduction of 37% and 16% in its total SET rate for the GEO and ISS orbits, respectively.
This analysis can be extended to encompass every gate within a cell library or a complex circuit. Such an approach facilitates the development of customized rules-based optimization and a SET-aware pin assignment during logic synthesis. For instance, in [40], this technique was applied in arithmetic benchmark circuits and up to 28% reduction on the SET rate was observed, depending on the circuit architecture and mission orbit. This optimization technique provides no area overhead and can be used along with other hardening techniques. Additionally, it does not impact the cell placement, and the net routing is impacted minimally and locally.
This optimization technique holds the potential to significantly enhance the benefits derived from the hardening techniques discussed earlier in this book, as it has been shown that the efficacy of layout and circuit-level techniques often exhibits input dependence. Consequently, pin assignment can be employed to maximize their efficiency. For example, this approach has been verified for the triple modular redundancy (TMR) optimization strategies discussed in [46]. In this work, four majority voter architectures were studied, and signal probability analysis was used to optimize TMR block insertion. While complex gate voters offered a smaller layout footprint, they exhibited a higher overall SET cross section due to increased charge collection area from upsized transistors. Conversely, basic logic gate architectures displayed a higher dependence on input signal probabilities due to logical masking effects. These findings suggest that incorporating an input dependence analysis into SET assessment can guide selective TMR block insertion in critical circuit nodes based on their signal probability distribution. This approach can optimize radiation hardening while minimizing area overhead and others.
6.3 Summary
In this chapter, the evaluation of circuit-level techniques is discussed, emphasizing the significance of reliability-driven synthesis in the VLSI design flow. The applicability of a detailed SEE characterization to support synthesis algorithms targeting SEE resilience is discussed. In this sense, a cell-based characterization can provide insights on the sensitivity of logic gates considering various device technologies (e.g., high performance vs. low power) and operating conditions (e.g., dynamic voltage scaling, input signal probability, etc.).
It was shown that the technology mapping process has a crucial role in determining the overall robustness of complex circuits. Since a single Boolean logic function can be implemented in various ways using different logic gates, logic synthesis in ASIC designs can benefit from incorporating logic transformations focused on reliability cost functions to mitigate the occurrence of transient pulses. For instance, the usage of complex logic gates might reduce the logical masking capabilities of a given combinational circuit.
Given the input dependence of the SEE sensitivity of logic circuits, an optimization methodology is proposed to improve the overall circuit hardness through pin swapping based on the signal probability. As shown in Chap. 5, the input dependence is attributed to the different driving capabilities and the influence of the layout design on the SET robustness. Given that the influence of layout design varies with LET, the relationship between input signal and gate SET cross section is also demonstrated to be LET dependent. The impact of adopting signal probability evaluation and pin assignment has shown the greatest cross-section reduction for low-particle LET. Considering the two-input gates, the signal with the lowest probability should be assigned to the input B for the NAND gate and to the input A for the NOR and XOR gates. For the three-input gates, different conclusions can be drawn based on the signal probability of the controllable input.
Pin assignment alone has the potential to reduce the SET rate, but it can also serve as an optimization technique to maximize the effectiveness of other layout and circuit hardening techniques. For example, a selective TMR block insertion can be developed based on the signal probability of the critical nodes and the SET cross section of several majority voter designs. The versatility of this optimization technique, grounded in input signal probability and input dependence analysis, offers a multitude of possibilities for achieving a more reliable and robust electronic system.
Highlights
The logical and physical synthesis processes of a VLSI circuit play a significant role in determining the performance characteristics of a VLSI circuit, from power, timing, and area consumption to the reliability against soft errors.
A Boolean logic function can be implemented in several ways during the technology mapping process, and therefore, the overall SEE susceptibility will be different for each design version.
Using complex logic gates can reduce the logical masking capabilities when compared with their counterpart design version using basic logic gates such as NAND, NOR, and INV gates.
The SET input dependence of logic gates can be used to optimize the overall circuit reliability when the signal probability of its input is considered.
Reliability-aware pin assignment can improve the overall robustness of a circuit on its own and, even more significantly, maximize the efficiency of several other hardening techniques without introducing any area overhead.
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