Radiation hardening techniques play a pivotal role in enhancing the resilience of VLSI circuits employed in radiation environments, most notably in critical applications such as in space technologies. Building upon the preceding chapter, some Radiation Hardening by Design (RHBD) techniques have been devised to effectively counteract the detrimental impact of radiation on electronic circuits, addressing diverse levels of abstraction ranging from circuit layout to system and software design. This chapter delves into an insightful analysis of the efficacy achieved through layout design techniques, namely Gate Sizing (GS), Transistor Stacking (TS), and Transistor Folding (TF). Moreover, it explores the utilization of asymmetric designs and the innovative Diffusion Splitting (DS) technique as means to augment the hardening efficiency while mitigating the associated area overhead.
5.1 Introduction
Radiation robustness can be accomplished through the meticulous application of reliability-aware logic and physical synthesis techniques within semi-custom designs, utilizing the established standard cell methodology [1‐4].
In essence, this approach enables the hardening of a circuit by selectively employing logic gates that minimize the SET generation or propagation in the most vulnerable nodes of a complex VLSI design. In semiconductor design, the fundamental constituents known as “standard cells” serve as the elemental building blocks for the physical realization of Boolean logic functions, including NAND, NOR, inverter, among others. By adopting a cell-based design methodology, the power and performance characteristics of these logic cells become readily accessible, enabling the application of various synthesis algorithms aimed at optimizing these metrics for the entire system design.
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A standard cell library contains a group of available standard cells that can be used to synthesize a whole system from the RTL description to the final layout physical design.
In [1], three selective node hardening techniques were examined when applied in the logic synthesis of different ISCAS85 benchmark circuits. Remarkably, the findings underscored the remarkable efficacy of these hardening techniques when deployed in standard cell-based VLSI designs. Furthermore, during physical synthesis, the integration of hardening strategies within the cell placement phase proves crucial in mitigating charge sharing effects and promoting pulse quenching effects in electrically interconnected combinational circuits [2‐4]. In a notable study by Du et al. [3], it was established that as the feature size diminishes, the influence of cell placement on the susceptibility of complex VLSI designs to soft errors becomes more pronounced due to the intricate multi-node collection process. Consequently, there exists an inherent necessity to explore selective node hardening strategies that can seamlessly be integrated into standard cell-based design methodologies. This section offers a comprehensive comparative analysis of the application of gate sizing and transistor stacking techniques within the context of a standard cell methodology, shedding light on their respective merits and limitations.
5.2 Part I—Gate Sizing and Transistor Stacking
5.2.1 Gate Sizing (GS)
The performance of circuits is directly influenced by the feature sizes of transistors, encompassing both the length (L) and width (W) of the device channel. Transistor and gate sizing techniques have gained widespread usage in numerous applications to optimize the trade-off between delay and power consumption [5, 6]. Figure 5.1 provides a simplified illustration of a transistor layout. The diffusion area, represented by the green layer, corresponds to regions where p-n junctions are formed, such as the source (S) and drain (D) of the transistor. The gate (G) of the device is depicted by the red rectangular shape, which represents the polysilicon layer. The blue color represents the metal 1 layer, while the yellow is a via, known as VIA0, that connects metal 1 layer to the diffusion layer.
Fig. 5.1
MOS transistor layout and its main feature sizing: width W and length L of the transistor channel
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The electrical characteristics of a transistor device are determined by the width (W) and length (L) of its channel. This is evident in the relationship governing the drain current \(I_D\), as depicted by Eq. 5.1. Altering the \(W/L\) ratio of transistors has a significant impact on the nodal capacitance and drive strength of the circuit, thereby influencing power consumption and propagation delay. In digital design, the length (L) of the transistor is typically set to the minimum available value dictated by the technology, as it is a process parameter constraint. Conversely, the width (W) of the transistor can be adjusted to fulfill the system design requirements. Increasing the width (W) reduces resistance, resulting in a higher drain current (\(I_D\)) and reduced propagation delay. However, this increase in width also leads to an augmented capacitance, consequently raising power consumption. Thus, the designer must seek the optimal sizing that aligns with the circuit requirements.
In addition to their influence on power consumption and propagation delay, the drive strength and nodal capacitance of a circuit also impact the radiation-induced transient currents. Therefore, gate sizing has also been employed to enhance the radiation robustness of VLSI circuits [7]. Let us analyze the radiation response of an inverter gate across different sizing scenarios (described in Table 5.1). The inverter, designed in the Complementary MOS (CMOS) logic style, consists of a single PMOS transistor in the pull-up network and a single NMOS transistor in the pull-down network. Figure 5.2 illustrates the transistor schematics, truth table, and the gate symbol of a CMOS inverter. The PMOS device is characterized by the channel width denoted as Wp, while the NMOS device is denoted as Wn. When an input signal at the low logic value (“0” or ground) is applied, the output of the inverter assumes a high logic level (“1” or power supply) and vice versa.
Fig. 5.2
Transistor schematics of a CMOS inverter, the truth table, and its symbol
Table 5.1
Gate sizing scenarios for the SET injection at an inverter
Wp (nm)
Wn (nm)
Scenario 1
630
415
Scenario 2
945
415
Scenario 3
630
622
Scenario 4
945
622
×
Scenario 1 corresponds to the minimum available sizing for an inverter gate in the 45 nm OpenCell NanGate library, a standard cell library for 45 nm technology [8]. Scenarios 2 to 4 involve multiplying the Wp and/or Wn values by a factor of 1.5. To explore the intricate relationship between gate sizing, nodal capacitance, restoring current, and the resulting Single-Event Transient (SET) pulse, electrical simulations are conducted using a SPICE circuit simulator, as described in Chap. 3. A double exponential transient current with consistent arbitrary SET parameters is injected across all sizing scenarios. The goal is to analyze the impact of gate sizing on the SET response. Figure 5.3 depicts the SET response for the injection campaign, with the input of the gate set to a low logic level. In this configuration, the NMOS device remains in the off state, while the PMOS device is responsible for maintaining the output signal at a high logic level. As a reference for this analysis, the SET response of the minimum sizing scenario (Scenario 1) is considered.
Fig. 5.3
SET injection at the output of a CMOS Inverter with different sizing scenarios when the NMOS device is sensitive
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In Scenario 2, where only Wp is increased by a factor of 1.5, the resulting SET pulse experiences a significant reduction in duration. However, the peak of the pulse does not reach half of the supply voltage, suggesting that it may be effectively masked in the subsequent gate stage. Conversely, in Scenario 3, when only Wn is upsized, the SET pulse remains nearly unchanged compared to the minimum sizing configuration in Scenario 1. Since the PMOS device is responsible for supplying the restoring current, increasing the width of the NMOS transistor (Wn) does not contribute to SET recovery in this case. In this analysis, the same parameters were utilized for defining the current source, resulting in the same amount of collected charge for all sizing scenarios. Nevertheless, by upsizing the transistor, a larger collection area is achieved, potentially enhancing the efficiency of charge collection. Therefore, if the charge collection mechanism were taken into account in this analysis, the resulting SET in Scenario 3 would likely be larger due to the increased collection efficiency facilitated by the augmented width (Wn) of the NMOS transistor. In Scenario 4, where both transistors are upsized, a similar response to Scenario 2 is observed. This outcome further confirms that, when the input signal is at a low logic level, the PMOS device should be upsized to mitigate radiation-induced transient pulses within the inverter gate.
Figure 5.4 presents the same analysis, but with the PMOS device in the off state, corresponding to an input signal at a high logic level. Notably, the SET pulse is significantly shortened only when the width of the NMOS transistor (Wn) is increased, as observed in Scenarios 3 and 4. Consequently, Scenario 4 emerges as the optimal sizing choice for enhancing the robustness of the inverter in both input cases. However, it is important to consider that upsizing transistors not only increases capacitance and restoring current but also enlarges the sensitive area. This can potentially compromise the reliability of the circuit by intensifying particle incidence probability and enhancing charge collection efficiency. Standard cell libraries provide cells with varying drive strengths, starting from the minimum-sized implementation (denoted by X1) and incrementing discretely to higher drive strengths like X2, X4, and so on. Due to the regular layout structure of standard cells and the availability of multiple drive strength options, gate sizing within the standard cell methodology is a discrete process. In a study by Cannon et al. [9], an RHBD cell library at 90 nm was evaluated under heavy-ion and high-energy proton irradiation, focusing on inverters, NAND, and NOR logic gates. Different drive strengths offered by the cell library were assessed, revealing that upsizing the cells effectively reduced the SET cross section for the inverter and NOR logic gates. However, in the case of the NAND2_X2 cell, the increased sensitive area dominated the SET sensitivity, outweighing the benefits of increased nodal capacitance and restoring current [9].
Fig. 5.4
SET injection at the output of a CMOS inverter with different sizing scenarios when the PMOS device is sensitive
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The efficiencies of layout-based techniques are closely dependent on the transistor technology. Therefore, they should be carefully analyzed through layout-based simulations and fault injection electrical characterization.
On the other hand, studies on FinFET-based circuits employing NAND and NOR gates have revealed similar SET sensitivity [10]. The symmetrical sizing of PMOS and NMOS transistors, achieved through strain engineering and width quantization in FinFET technologies, results in comparable drain area and restoring current, thereby leading to equivalent susceptibilities to soft errors for both gate types. In this chapter, gate sizing is evaluated using the prediction methodology elucidated in Sect. 3.4. By employing a comprehensive multi-physics prediction methodology, the complex relationship between charge collection efficiency and electrical characteristics involved in layout-based radiation hardening techniques is examined, providing insights into their impact on the Single-Event Effects (SEE) cross section.
5.2.2 Transistor Stacking (TS)
An alternative approach to gate sizing is the utilization of transistor stacking (TS) to enhance the nodal capacitance [1]. Stacking devices is a well-known RHBD technique used for SEU immunity in SOI designs [11, 12]. To illustrate the principle behind this hardening technique, Fig. 5.5 depicts the transistor schematics of an inverter and a simplified representation of the NMOS transistors at the device level in a SOI technology. Instead of employing two transistors as shown in Fig. 5.2, the TS-based CMOS inverter incorporates four transistors, with the additional transistors connected in series with the original ones.
Fig. 5.5
Application of transistor stacking in an inverter design based on a SOI technology and the representation of a heavy-ion ionization. The electron-hole pairs generated within the insulator are omitted due to its negligible contribution to the SEE effects
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The use of shallow trench isolation (STI) and buried oxide (BOX) in SOI structures effectively mitigates charge sharing between stacked transistors, significantly enhancing the overall resilience to soft errors [11]. In a TS inverter employing SOI technology, if an incident particle strikes only transistor N2, the resulting SET is unable to propagate to the output since transistor N1 is in off state and behaves as an open circuit. Hence, for a soft error to manifest in the circuit, a single particle impact must deposit a sufficient charge in both stacked devices, or at least in the nearest one to the output. Recent studies have demonstrated that by exclusively utilizing stacked NMOS devices in SOI latch designs, the SEU rate can be improved by over 80% [13]. In contrast, bulk devices experience charge sharing effects among adjacent transistors. Nonetheless, they still benefit from increased nodal capacitance and the masking effect provided by stacked devices. Moreover, transistor stacking enables power consumption reduction due to lower leakage current compared to single transistors of the same size [14]. In terms of power consumption, transistor stacking has been shown to outperform gate sizing while maintaining similar area efficiency [1]. However, it is important to note that connecting transistors in series, as done in the stacking technique, increases the effective (dis)charging resistance, leading to increased delay and potential degradation of circuit performance.
One of the advantages of gate sizing and transistor stacking is their compatibility with both full-custom designs and standard cell libraries. As explained earlier, a cell library comprises various logic functions implemented in different drive strengths and with varying numbers of input signals. Consequently, a 4-input NAND gate (NAND4) can function as a 2-input NAND gate (NAND2) by incorporating stacked devices, with the additional inputs connected to the original inputs, as illustrated in Fig. 5.6. However, the transistor stacking technique is exclusively applied in the pull-down network, while in the pull-up network, the additional transistors are connected in parallel to enhance the overall driving strength. Similarly, employing a 4-input NOR gate enables the creation of a 2-input NOR gate with PMOS stacked devices.
Fig. 5.6
Using 4-input NAND gate to achieve stacking transistors for a 2-input NAND function with standard cell libraries
×
The following section examines the impact of circuit layout on the deposition and charge collection process, specifically examining the radiation hardening effectiveness of gate sizing and transistor stacking within a cell-based methodology. With a focus on low-power reliable applications, the analysis centers on striking a balance between power consumption and resilience against radiation-induced effects, particularly SETs. As it will be shown, it is of significant importance the exploration of the input dependency associated with each technique, which can be leveraged to enhance the radiation reliability of hardened standard cell libraries while minimizing area, power, and performance overhead.
5.2.3 Comparison of Power and Area Overhead
In terms of power consumption, adopting RHBD techniques often leads to an increase in power, particularly in terms of static power consumption, which is considered in this analysis. Figure 5.7 illustrates the static power consumption for the NAND and NOR gates when employing gate sizing and transistor stacking techniques. For both standard cells, gate sizing demonstrates the highest increase in power consumption, with a factor of 2. This can be attributed to the increased leakage current associated with the adoption of larger transistors.
Fig. 5.7
Static power consumption estimation for unhardened, gate sizing, and transistor stacking implementations of the NAND and NOR gates
×
In contrast, transistor stacking exhibits lower power consumption compared to gate sizing. This is due to the reduction in leakage current resulting from the transistor stacking effect. It is important to note that when adopting transistor stacking using standard cells, the stacked devices for the NAND and NOR gates are the NMOS and PMOS transistors, respectively. Since NMOS transistors in the pull-down network generally have higher leakage current than PMOS transistors, the reduction in static power consumption is more significant for the NAND gate, which incorporates stacked NMOS devices. As a result, the NAND gate consistently displays the lowest static power consumption among the three designs considered in this analysis.
Layout-based hardening techniques can negatively impact the performance of the circuits, leading to increase in power consumption or propagation delays.
5.2.4 Impact on the SET Cross Section
Figure 5.8 displays the log–log representation of the SET cross-section curves for the NAND gates: unhardened, GS-based, and TS-based design versions. The cross section is calculated for each input signal combination, and the arithmetic mean for each particle LET is presented. At a particle LET of 2.5 \(\mbox{MeV.cm}^2/\mbox{mg}\), gate sizing achieves the highest reduction in SET cross section, approximately 78%, while transistor stacking results in a reduction of around 24%. The effectiveness of both techniques in enhancing radiation robustness diminishes as the particle LET increases. Despite the increase in drain area, gate sizing still leads to a reduction in the overall SET cross section, albeit only 3%, for a particle LET of 78 \(\mbox{MeV.cm}^2/\mbox{mg}\).
Fig. 5.8
Average of the SET cross section for each input signal the NAND logic gate: minimum sized (unhardened), using gate sizing; and transistor stacking
×
Conversely, the transistor stacking technique increases the SET sensitivity of the circuit by approximately 11.7%. This rise in cross section is attributed to the enlarged layout area and drain regions resulting from these layout-based hardening techniques. For high particle LET, the dominant factor affecting circuit reliability is the enhanced charge collection efficiency facilitated by the larger transistors. Similar trends can be observed in the SET cross-section curves of the NOR gates depicted in Fig. 5.9. However, both techniques exhibit higher efficiency compared to the NAND gates. For instance, transistor stacking achieves an SET cross-section reduction of approximately 60% for the TS-based NOR gate under particles of 2.5 \(\mbox{MeV.cm}^2/\mbox{mg}\), twice the reduction observed for the NAND gate. This discrepancy can be attributed to the reduced difference in drain area between the stacked-device NAND and NOR gates and the interplay between the driving capabilities of the pull-up and pull-down transistor networks in the two gates. To gain a deeper understanding of these results, a closer examination of the input signal and layout design of each gate is necessary.
Fig. 5.9
Average of the SET cross section for each input signal the NOR logic gate: minimum sized (unhardened), using gate sizing; and transistor stacking
×
In Fig. 5.10, the SET cross section \(\sigma _{SET}\) for each input signal combination is shown for the NAND gate under a particle LET of 78 \(\mbox{MeV.cm}^2/\mbox{mg}\). The input signal combination (0, 0) exhibits the lowest sensitivity, while the input combination (1, 1) is the most SET sensitive for the NAND gate. When the input signal combination (0, 0) is applied to a NAND gate, both NMOS transistors are turned off, and the two PMOS transistors supply the output signal. This configuration leads to lower sensitivity due to the increased capacitance in the two series-connected NMOS transistors and the strong recovery current from the two parallel-connected PMOS transistors. Conversely, for the NOR gate, which is the complement of the NAND gate, the opposite behavior can be observed in Fig. 5.11. In this case, the input combination (0, 0) is the most SET sensitive, while the input combination (1, 1) is the least sensitive.
Fig. 5.10
SET cross section for each input signal combination of the NAND gate under 78 \( \mbox{MeV.cm}^2/ \mbox{mg}\)
Fig. 5.11
SET cross section for each input signal combination of the NOR gate under 78 \( \mbox{MeV.cm}^2/ \mbox{mg}\)
×
×
Notice that for the most sensitive input combination, both techniques provide a higher cross section than the unhardened design, especially the transistor stacking. In order to explain why the TS technique worsened the reliability in some input scenarios, it is important to analyze the transistor schematics and its equivalent driving strength of each transistor network. In Fig. 5.12, the transistor schematics and the equivalent driving strength of each NAND design are depicted. The unhardened design (NAND2_X1) has its equivalent pull-up and pull-down driving strengths labeled as \(Wp_{eq}\) and \(Wn_{eq}\), respectively. Based on the parallel and series associations, an estimation of the driving strength for the GS-based and TS-based designs is provided. As expected, the GS-based design (NAND2_X2) exhibits twice the driving strength of the unhardened design for both the pull-up and pull-down transistor networks. However, in the TS-based design (NAND4_X1), which is logically used as a 2-input NAND gate, only the pull-up network experiences an increase in driving strength, while the pull-down network has its strength reduced by 1.5 times. This explains the observed results for the input combination (1, 1) in Fig. 5.10.
Fig. 5.12
Transistor schematics and the equivalent driving strength of NAND2_X1 (unhardened), NAND2_X2 (gate sizing) and NAND4_X1 (transistor stacking)
×
Considering the worst-case input scenario for the transistor-stacked NAND (NOR) design, where all radiation-sensitive transistors are PMOS (NMOS) devices, the 4-stacked NMOS transistors in the NAND pull-down network serve to provide the restoring current to counteract the parasitic SET pulse from the PMOS devices. This configuration helps explain the increased cross section observed for certain input scenarios in Figs. 5.10 and 5.11, particularly when the input combination involves all ones or zeros.
However, transistors in series provide less current drive due to the increased effective resistance, leading to performance degradation and also larger SET pulse width and increased cross section. Additionally, the total drain area of PMOS devices in the TS-based NAND design is twice the area of the unhardened one, inducing a higher collected charge. These can also be confirmed in Fig. 5.13, which the SET pulse width measurements for each technique applied on the NAND gate are provided. The unhardened and gate-sized designs present similar pulse width mean and maximum, while the transistor stacking design can have a maximum SET pulse width more than 2\(\times \) larger than the unhardened design. As expected from the previous results, the transistor stacking technique increases the overall pulse width mean due to the reduced drive strength of the stacked devices. The similar pulse width features between the unhardened and gate sizing design can be attributed to the balance between the increase of the recovering drain current and the collected charge in the upsized transistors.
Fig. 5.13
SET pulse width measurements for the NAND and NOR gates under 78 \( \mbox{MeV.cm}^2/ \mbox{mg}\)
×
Another observation from Figs. 5.10 and 5.11 is that for the TS-based designs, no SET is observed for the input (1, 0) and the input (0, 1) in the NAND and NOR gates, respectively. To understand this result, we need to have a look in the transistor stacking structure of each gate. In Fig. 5.14, the pull-down network of the TS-based NAND is shown, containing the 4-stacked NMOS transistors. Considering the input (1, 0), which no SET was observed in the output, the sensitive transistors are placed next to the ground supply and far from the output. In this case, whenever a particle hits the off transistor (red cross), the SET pulse is electrically masked by the 2-stacked transistor series before reaching the output of the gate. On the other hand, for the input (0, 1), the off transistors are placed just next to the output of the gate. Thus, whenever a particle deposits sufficient charge near the off transistor next to the output, one SET will be observed. This same analogy can be drawn to the NOR gate where the 4-stacked PMOS transistors will mask any SET from the transistors placed next to the VDD supply. In summary, when adopting transistor stacking: (1) the transistors placed far from the output of the gate will be very likely hardened to any SET due to the electrical masking effect inherent of the stacking structure; (2) the worst-case input scenario is worsened due to the reduced driving capability of the series transistors in the stacking structure.
Fig. 5.14
Pull-down transistor network of the TS-based NAND gate and the implications of input (1, 0) and (0, 1). Particle hits are represented by a red cross
×
5.3 Part II—Transistor Folding (TF) and Diffusion Splitting (DS)
The transistor folding layout technique is a common practice in both digital and analog circuit designs, aimed at enhancing performance and regularity in VLSI circuits [15]. For instance, when larger transistors are required, exceeding the fixed cell height of a given circuit design, the folding technique is employed. This method involves connecting parallel transistors with reduced channel width to achieve a larger overall width. For a transistor with a channel width \( W \), the same \( W/L \) ratio, and thus the same drive strength, can be achieved by connecting \( n \) transistors with channel widths equal to \( W/n \). Figure 5.15 illustrates the principle of folded transistor layouts, particularly in the case of a double-finger transistor. This layout technique divides the drain and source area into smaller partitions, potentially resulting in a significant reduction in drain area. For example, instead of using the SDS connection shown in Fig. 5.15, the circuit designer could opt for the DSD connection and limit the reduction in drain area.
Fig. 5.15
Transistor folding layout technique
×
In terms of radiation effects, this technique offers a reduced collecting drain area while preserving the same drive strength. The transistor size of the folded designs can be computed using Eq. 5.2, where \( W_{F} \) represents the width of each folded transistor, \( N_{F} \) denotes the number of fingers, and \( W \) stands for the transistor width in the original design.
$$\displaystyle \begin{aligned} W_{F} = \frac{1}{N_{F}} \times W. {} \end{aligned} $$
(5.2)
The transistor folding technique can be combined with other hardening techniques such as gate sizing or dummy transistors/gates. The work in [16] was the first to propose transistor folding along with gate sizing to harden a circuit against both SEUs and SETs. A 3D mixed-mode TCAD (Technology Computer-Aided Design) simulation was carried out to analyze the SET pulse characteristics considering alpha particle and heavy ions hit on the center of the drain junctions [16]. Different from the sizing approach, which increases the circuit drive strength at the cost of increased drain area, transistor folding is able to reduce the transistor drain area while keeping the same drive strength. The transistor sizing was able to improve the robustness only for low-energy particles, while the transistor folding showed also improvement when considering high-energy particles [16, 17]. In [18], different well structures and layout topologies were studied to evaluate the Propagation-Induced Pulse Broadening (PIPB) effect in inverter chains. Accordingly, a double-finger inverter chain was compared against a single-finger inverter chain. In agreement with [16], the heavy-ion results show a reduction on the overall SET pulse width, but minimum influence in the PIPB effect. Inverter chains hardened with guard rings were also evaluated using single- and double-finger layout configurations with laser irradiation in [19]. Again, results showed an insignificant pulse broadening factor for the folded inverter chain; however, a wider SET pulse width average was observed in this case [19]. The authors attributed this to the larger spacing between the drain junctions and the guard rings in the folded design, which limits the charge collection reduction provided by the guard rings. Most studies have focused on inverter chain analysis, primarily with 2-finger layout configurations. In this section, transistor folding is applied to inverter, NAND, and NOR gates, with analysis conducted through layout-based predictive Monte Carlo simulations [17, 20].
The target circuit layouts were fully designed following a commercial Process Design Kit (PDK) in a bulk 65 nm technology. Additionally, all circuits are compatible with a standard cell library approach. Minimum width, spacing, and alignment/symmetry of each layer are carefully addressed to provide compatibility among the standard cells of the target technology. The cell height is set to 13 tracks of metal pitch, i.e., \(2.6\,\upmu \)m high. To provide flexibility in cell routing, the metal 1 (M1) is primarily used for the intracell connections, except for some cases in which metal 2 (M2) is used horizontally. The PMOS transistor width is 760 nm, while the NMOS transistor width is 540 nm. To analyze exclusively the impact of the folded layouts, the equivalent gate sizing was kept the same for all cases. After all circuit designs are DRC (Design Rule Check) clean, LVS (Layout Versus Schematic) checked, and logic and electrical characterization is performed, the collecting drain area information can be extracted from the GDS (Graphical Design System) format file and submitted to the MC-Oracle tool [21]. All circuits were driving a fan-out 1 (FO1), i.e., an inverter was coupled to its output signal. Only the SET pulses with peak voltage higher than 0.6 V (half the supply voltage) are considered for the cross-section calculation. In addition to the double-finger designs (Fig. 5.15), quadruple-finger layout configurations are also considered in this work as shown in Fig. 5.16. However, one of the drawbacks of increasing the number of fingers in the folding technique, while maintaining the same gate sizing, is the increase in layout area due to the misuse of the fixed cell height. Thus, to address the area overhead associated with multiple-finger designs, Diffusion Splitting (DS) layout technique was first proposed in [17] and proven to enhance the radiation robustness of the digital circuits. As shown in Fig. 5.16, instead of using a single strip of active diffusion, a 2-row stacked diffusion transistor can be used. In [22], TCAD simulations demonstrated the efficacy of DS-based layouts, termed Splitting Active Area (SAA) layouts by the authors, in reducing charge collection efficiency, particularly for PMOS devices. To deepen this analysis, the impact on the in-orbit SET rates for heavy ions and protons is also presented later in this chapter.
Fig. 5.16
Standard quadruple-finger folded transistor layout vs. folded transistor layout with Diffusion Splitting (DS) technique in which the diffusion strip is split into two strips and placed vertically aligned within each other
×
Notes
Besides reducing the area overhead of the folding technique, Diffusion Splitting (DS) technique improves the metal connection routability maintaining the same W/L ratio and the number of gate fingers.
5.3.1 Impact on the SET Cross Section
For the three cells analyzed, the double-finger layout configuration exhibited an area increase of approximately \(1.5\times \) the original unhardened single-finger layout area. An area increase around \(2.5\times \) is expected when using quadruple-finger layout designs. However, if DS is used, the area overhead for the four-finger designs can be reduced to the same observed in the two-finger designs, that is, approximately \(1.5\times \) greater than the original designs. Thus, DS provides an area reduction of 36% and 42% for the four-finger inverter and NAND/NOR cells, respectively. Once again, both NAND and NOR gates provide the same layout area in the original and folded designs due to the layout design regularity inherent of standard cell libraries. In Fig. 5.17, the simplified layouts of the NAND designs containing only M1, diffusion, and poly layers are shown. In standard cell methodology, a fixed cell height is defined to provide regularity. Thus, as the number of fingers is increased, the cell width is increased and, consequently, the cell layout increases. As the transistor sizing is kept the same, the DS can be applied to reduce the impact on the layout area, as shown in Fig. 5.17. For the sake of compactness, the layout designs for the inverter and NOR gates are omitted.
Fig. 5.17
Simplified layout design of NAND F0 (no folding, unhardened), NAND F2 (2-finger design), NAND F4 (4-finger design), and NAND F4S (4-finger design with diffusion splitting). For clarity, only the metal1 (blue), active diffusion (green), and poly layers (red) are shown
×
The SET cross section \(\sigma _{SET}\) for the inverter designs under particle LET of 78.23 \(\mbox{MeV.cm}^2/\mbox{mg}\) is shown in Fig. 5.18. The folded designs have shown similar \(\sigma _{SET}\) for input 1 and input 0. Thus, using transistor folding may reduce the SET sensitivity dependence on the input signal in the inverter design at high LET. On average, the folded designs provide lower sensitivity than the unhardened design with the greatest \(\sigma _{SET}\) reduction for the 2-finger layout configuration, approximately 42%. The 4-finger inverter shows improvement solely for the input 1; however, despite the area reduction, DS also reduced the \(\sigma _{SET}\). To analyze the folding impact for low particle LET irradiation, Fig. 5.19 presents the SET cross section for the inverter designs considering heavy ions with LET \(=\) 5.43 \(\mbox{MeV.cm}^2/\mbox{mg}\). In this case, the greatest \(\sigma _{SET}\) reduction is observed for the 4-finger inverter with DS, about 37%.
Fig. 5.18
SET cross section for the inverter designs under LET \(=\) 78.23 \( \mbox{MeV.cm}^2/ \mbox{mg}\) considering input 0, input 1, and the mean value
Fig. 5.19
SET cross section for the inverter designs under LET \(=\) 5.43 \( \mbox{MeV.cm}^2/ \mbox{mg}\) considering input 0, input 1, and the mean value
×
×
It can be observed that, for low LET, the \(\sigma _{SET}\) reduces with the increase of the number of fingers \(N_{F}\), in agreement with 3D TCAD results obtained in [16]. As \(N_{F}\) increases, the collecting regions are reduced and sparsely distributed along the layout, and then the charge sharing at low LET is limited. Thus, less folded transistors are affected by a single particle hit, leading to an improvement in the efficiency of the technique in reducing the \(\sigma _{SET}\).
Considering the NAND designs, Fig. 5.20 presents the SET cross section \(\sigma _{SET}\) for particle LET equals to 78.23 \(\mbox{MeV.cm}^2/\mbox{mg}\). Except for the 2-finger design, the folded designs provided a higher mean \(\sigma _{SET}\). At high LET, the hardening efficiency of folded transistors is limited due to the complex input dependence observed on the cross section. The folded NAND designs show a stronger input dependence than the original unhardened version, leading to a similar or lower \(\sigma _{SET}\) only for inputs (0, 0) and (0, 1). The worst-case input scenario for NAND gates is the input (1, 1), and, in this case, transistor folding exacerbates the SET sensitivity up to approximately 62% in the 4-finger design.
Fig. 5.20
SET cross section for the NAND designs at LET \(=\) 78.23 \( \mbox{MeV.cm}^2/ \mbox{mg}\) for each input signal and the mean value
×
As observed for the gate sizing and transistor stacking designs in the previous section, the layout-based hardening techniques can worsen the SET robustness in the worst-case input scenario. For input (1, 1), all PMOS devices are sensitive to a particle hit, and besides the lower restoring capability of NMOS devices, PMOS transistors collect more charge due to its larger drain area [23]. Similarly, in the NOR case, the input (0, 0) is the worst-case input scenario, and it shows increased \(\sigma _{SET}\) when adopting folded transistors as shown in Fig. 5.21. To reduce the increased sensitivity at the worst-case input scenarios, transistor folding can be applied only in the pull-down (or pull-up) network to balance the overall SET sensitivity. The asymmetric designs are also considered in this chapter, and it is discussed in the following section. Despite the poor hardening performance for high particle LET, the folded designs have shown great reduction on the overall SET cross section for low LET. Considering the NAND design under particle LET of 5.43 \(\mbox{MeV.cm}^2/\mbox{mg}\) shown in Fig. 5.22, the 4-finger design showed the lowest mean \(\sigma _{SET}\), and similar sensitivity is obtained with DS. Thus, it is important to note that, for low LET, increasing the \(N_{F}\) also improves the overall SET cross section \(\sigma _{SET}\) as observed for the inverter design.
Fig. 5.21
SET cross section for the NOR designs at LET \(=\) 78.23 \( \mbox{MeV.cm}^2/ \mbox{mg}\) for each input signal and the mean value
Fig. 5.22
SET cross section for the NAND designs at LET \(=\) 5.43 \( \mbox{MeV.cm}^2/ \mbox{mg}\) for each input signal and the mean value
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×
However, the worst-case input scenario is still worsened by the technique, for instance, in the F2 NAND design. The full understanding of the impact on the SET cross section can be better visualized through the curves in Fig. 5.23. As previously mentioned, for high LET, the folded designs may exhibit similar or even worse radiation robustness than the original unfolded version (F0 designs). However, as the LET decreases below 10 \(\mbox{MeV.cm}^2/\mbox{mg}\), the folded designs start to demonstrate improved or comparable cross sections to the observed for the F0 designs. For LET lower than 10 \(\mbox{MeV.cm}^2/\mbox{mg}\), the 4-finger design (F4) is preferred. Except for the 2-finger NAND (F2), all other folded designs provided a higher threshold LET than the unfolded design.
Fig. 5.23
Log–log representation of the mean SET cross-section curves for the NAND designs (F0: unfolded, F2: 2-finger, F4: 4-finger, F4S: 4-finger design with diffusion splitting). No event was observed in the F4 and F4S designs (triangle and rhombus curves) for LET lower than 5.43 \(\mbox{MeV.cm}^2/\mbox{mg}\)
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5.3.2 Asymmetric Designs
As observed in the last subsection, transistor folding can induce a higher SET cross section for the worst-case input scenario of the NAND and NOR circuits. Thus, in this section, a deep analysis is provided in order to enable a better usage of the TF technique. Figure 5.24 presents the transistor network of a NAND gate along with its corresponding truth table. For the worst-case scenario, highlighted in red, the off transistors, which are sensitive to particle hits, are issued from the pull-up network, i.e., PMOS devices.
Fig. 5.24
Transistor network of an NAND gate and its truth table. On state and off state are indicated for the transistors considering the worst-case input scenario, i.e., input (1, 1)
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So far, the folding technique has been equally applied to both pull-up and pull-down networks. However, in order to investigate the impact of asymmetric designs, this analysis explores two specific configurations: the 2-finger design and the 4-finger design with drain/source (DS) adopting folding in only one of the networks, while the other network remains unfolded. By examining the effects of asymmetric designs, a more comprehensive understanding of the impact of transistor folding on SET cross sections can be obtained. This analysis aims to determine the effectiveness of selectively applying the folding technique to either the pull-up or pull-down network, taking into account the specific characteristics of the worst-case scenario.
The folding technique was applied only in the NMOS devices for the NAND gate, and only in the PMOS devices for the NOR gate. The SET cross sections are shown in Fig. 5.25 for each design considering only the worst-case input scenario, i.e., the input combination (1, 1) and (0, 0) for the NAND and NOR, respectively. The number indicates the fingers, N/P indicates when only NMOS/PMOS devices are folded, and S indicates when diffusion splitting is adopted. For instance, the F4NS circuit is the 4-finger design with only NMOS devices folded and with diffusion splitting. This nomenclature is used in the remaining of this chapter for the sake of compactness. For the LET \(=\) 78.23 \(\mbox{MeV.cm}^2/\mbox{mg}\), the asymmetric designs were able to improve the SET robustness of the circuits. The greatest reduction on the cross section was observed for the 4-finger designs. The NAND F4NS circuit provides a reduction of 26.5% when compared to the NAND F4S circuit, while the NOR F4PS circuit has approximately 29.7% of reduction compared to the NOR F4S.
Fig. 5.25
SET cross section for symmetric and asymmetric designs of 2-finger and 4-finger with diffusion splitting of NAND and NOR gates in the worst-case input scenario, i.e., input (1, 1) and input (0, 0), respectively
×
However, when adopting the asymmetric designs, not only the worst-case input SET cross section is affected but in all input scenarios. It can be seen in Figs. 5.26 and 5.27 in which the SET cross section \(\sigma _{SET}\) for each input signal and the mean value are shown for the NOR and NAND gate, respectively.
Fig. 5.26
SET cross section for the NOR designs at LET \(=\) 78.23 \( \mbox{MeV.cm}^2/ \mbox{mg}\) for each input signal and the mean value
Fig. 5.27
SET cross section for the NAND designs at LET \(=\) 78.23 \( \mbox{MeV.cm}^2/ \mbox{mg}\) for each input signal and the mean value
×
×
After examining the results of the asymmetric designs for NOR and NAND circuits, it is evident that there is a slight increase in the cross section for specific input combinations, such as (0, 1), (1, 0), and (1, 1). For the NOR F4PS circuit, the mean SET cross-section reduction is approximately 13%, while the NOR F2P circuit demonstrates a similar mean SET cross section to the NOR F2 circuit. Similar observations can be made for the NAND designs, as depicted in Fig. 5.27. These findings reinforce the importance of considering input dependencies when implementing radiation hardening techniques in digital logic circuits.
5.3.3 Voltage Variability
In addition to radiation effects, electronic circuits are also vulnerable to dynamic environmental variability, including voltage fluctuations caused by voltage drops and di/dt noise in current derivatives [24]. Previous studies have highlighted that voltage variability can significantly impact circuit reliability, particularly in harsh environments where radiation effects are present [25, 26]. For instance, in [25], it was demonstrated that voltage variability reduces the threshold LET for various XOR topologies in FinFET and Trigate devices. Moreover, [26] observed a decrease in the electrical masking capability of gates and an increase in the SET pulse width under voltage variability conditions. Therefore, to comprehensively assess the impact of transistor folding, diffusion splitting, and asymmetric designs, the influence of voltage variability on SET cross section is evaluated and shown in Fig. 5.28.
Fig. 5.28
SET cross section considering a voltage drop of 10% over the nominal supply voltage and a particle LET of 5 \(\mbox{MeV.cm}^2/\mbox{mg}\). The percentage increase \(\varDelta \sigma _{SET}\) in the cross section is also shown in orange line
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The IR drops due to the parasitic resistance of the power grids can lead to \(\pm \)10% variation on the supply voltage. Accordingly, all circuits were analyzed considering a voltage drop of -10% of the nominal supply voltage of the technology, i.e., 0.12 V. The SET cross section and the variation \(\varDelta \sigma _{SET}\) (in %) are shown for each circuit in Fig. 5.28. As expected, a reduction on the supply voltage of the circuits reduces the driving capability and consequently reduces the recovery efficiency, leading to a higher \(\sigma _{SET}\). The usage of diffusion splitting technique induces insignificant impact on the circuit robustness to voltage variability as similar SET cross sections are obtained for the F4 and F4S circuits. However, for the 3 logic gates (inverter, NAND and NOR), the F4 and F4S circuits showed the greatest \(\sigma _{SET}\) increase, ranging from 50% to 70%. Thus, as the number of fingers is increased, the circuit becomes more sensitive to the voltage drops. However, the asymmetric designs have shown to reduce the impact of voltage variability on the SET cross sections. Considering only the inverter designs, the F4S circuit shows the lowest \(\sigma _{SET}\) at nominal voltage, but it is the most sensitive to voltage drops, along with the F4 circuit. On the other hand, the F2 circuit provides the lowest \(\sigma _{SET}\) at -10% of the supply voltage, and also the lowest variation on \(\sigma _{SET}\).
For the NAND gate, the F4 circuit provides the lowest \(\sigma _{SET}\) at nominal voltage, but it increases up to 66% with 10% reduction on the supply voltage. In this case, the unhardened circuit is the least sensitive design to voltage variation, leading to approximately 24% of increase in the \(\sigma _{SET}\). However, under voltage drop, the lowest \(\sigma _{SET}\) is observed for the asymmetric design F4NS circuit. Compared to the unhardened NAND circuit, when the voltage fluctuation is considered, the F4NS reduced the \(\sigma _{SET}\) up to 35%. For the NOR gate, similarly to the NAND gate, the F4 circuit provides the lowest \(\sigma _{SET}\) at nominal voltage, but high sensitivity to the voltage drops, resulting in approximately 49% increase in the \(\sigma _{SET}\). However, it still provides the lowest \(\sigma _{SET}\) during voltage fluctuation. The diffusion splitting used in F4S increased its cross section, but it still provides a lower \(\sigma _{SET}\) than the F2 circuit, with the same area overhead. This initial analysis indicates that variability should be carefully taken into consideration when adopting layout techniques as it is critical for circuit-based techniques.
Process, Voltage, and Temperature variability, also known as PVT variability, will also affect the sensitivity of your design and should be considered in the design phase.
5.3.4 Impact on the In-Orbit SET Rate: LEO and ISS Orbits
To study the impact of adopting these techniques in a radiation environment, the in-orbit SET rates were estimated for the Low-Earth Orbit (LEO) and International Space Station (ISS) orbits. The OMERE software was used based on the SET cross-section curves calculated with the current database provided by MC-Oracle. OMERE is a tool dedicated to the analysis of space environment and radiation effects on electronics developed by TRAD and CNES [27]. The Integral Rectangular Parallelepiped (IRPP) approach is used to predict the SET rate, i.e., it is calculated by the convolution of the heavy-ion cross-section data with the particle flux in the aforementioned orbits. This approach is a standard method specified by the European Cooperation for Space Standardization (ECSS) [28]. The NASA AP8MIN trapped radiation model is used for the proton fluxes under solar minimum conditions [29]. For the Galactic Comic Rays (GCR) fluxes, the international standard ISO 15390 model is used [30]. A fixed shielding of 1 \(\mbox{g/cm}^2\) is considered. The calculated heavy-ions SET rates are shown in Fig. 5.29. Firstly, it can be noticed that all folded designs exhibit lower rates than its unhardened version (F0 circuit) for both orbits. In the case of the inverter, the F4S circuit provides the lowest rate with a reduction of approximately 82% and 77% in the ISS and LEO orbits, respectively. Similarly, for the NOR gate, the F4S showed the lowest SET rate. The folded transistor and diffusion splitting provided about 66% and 55% of reduction on the SET rate for the ISS and LEO orbits, respectively.
Fig. 5.29
Heavy-ions SET rate estimated with OMERE [27] for each circuit and its hardened version considering the LEO (800 km, 98\({ }^\circ \)) and ISS (400 km, 51.64\({ }^\circ \)) orbit. The SET cross-section average of each input signal is used
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On the other hand, the F2 circuit is expected to have a lower rate for the NAND gate. Although the cross-section calculations were performed for heavy ions, the protons are expected to dominate the SEE rates in the LEO and ISS orbits. Due to its improved accuracy when compared to analytical models, the METIS method [31‐33] was used to predict the proton-induced SET cross-section curves from the heavy-ions data. The sums of the SET rate induced by heavy ions and protons are shown in Fig. 5.30. As expected, the overall SET rate increased considerably. However, in this case, the F4 and F4S circuits are no longer the most hardened designs. The F2 circuits have shown the lowest rate for the inverter and NAND gate, for both orbits. For the NOR gate, the asymmetric design F2P provided the lowest rate, about 10% reduction for the two orbits. Except for the F2N, one can notice that whenever the asymmetric design approach is adopted, a reduction on the overall SET rate is observed.
Fig. 5.30
Total SET rate estimated with OMERE [27] for each circuit and its hardened version for the LEO (800 km, 98\({ }^\circ \)) and ISS (400 km, 51.64\({ }^\circ \)) orbits considering heavy ions and protons. Proton-induced SET rates are estimated with the METIS method [31]. The SET cross-section average of each input signal is used
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5.3.5 Transistor Scaling and Angular Dependence
As the demand for improved performance and low power in critical systems grows, future missions are considering advanced technology nodes. However, the effectiveness of hardening techniques may diminish with transistor scaling, as close proximity increases charge sharing effects. Nevertheless, in FinFET technologies, the three-dimensional structure of the transistor impacts on the charge collection process, and a reduction on the charge sharing effects might be expected as shown in [34]. Additionally, adoption of SOI technology could significantly enhance hardening efficiency by eliminating diffusion contributions to charge collection [35].
Regarding angular effects on charge collection, research indicates that folded transistors exhibit minimal angle dependence [36]. It was shown that only the NMOS transistors experienced an increase in collected charge for angled strikes. For the worst-case scenario, in which the particle strikes the center of the drain area with a tilt angle of 60\({ }^{\circ }\), the total collected charge of a 4-finger NMOS transistor can be 20% higher than the collected charge in the original design, without transistor folding. Thus, a very weak angle dependence can be expected in the SET cross section of the folded designs, especially for low LET due to the reduced charge sharing between adjacent devices. Further, according to [37], deeply scaled CMOS technologies present a marginal difference on the overall charge sharing effect between normal and angled strikes.
5.4 Summary
Physical layout design influences the main SEE mechanisms in VLSI circuits such as charge collection and charge sharing effects. Accordingly, RHBD techniques can be adopted at layout level to improve the radiation robustness of electronic circuits. In this chapter, three RHBD techniques exploring layout modifications were analyzed under heavy ions: gate sizing, transistor stacking, and transistor folding. Firstly, the gate sizing and transistor stacking were studied based on pre-designed standard cells. The idea is to investigate how conventional standard cell libraries can be used to maximize the reliability of VLSI systems under radiation effects. Besides the area and leakage current increase, both techniques were able to provide a reduction on the overall SET cross section, especially for low particle LET. The NOR gate shows the greatest improvements on the SET cross section even though transistor stacking can increase the maximum SET pulse width to 2\(\times \) wider than the original design. Gate sizing shows the best trade-off between area, power, and reliability. However, the hardening efficiency of transistor stacking is strongly dependent on the input signal of the gate. This is a reflection to the fact that, in the stacking structure, the transistors placed far from the output of the gate will be likely unable to induce a SET pulse in the output due to the electrical masking effect. Thus, according to the application, this technique can possibly outperform gate sizing. In the next chapter, signal probability will be used in order to enhance the hardening efficiency of RHBD techniques.
After understanding the implications of adopting gate sizing and transistor stacking, the efficiency of transistor folding layout in improving the SET immunity of digital circuits was presented. The results have shown that folded designs can provide lower SET cross section in addition to the higher threshold LET than the observed for the unfolded designs. The number of fingers was also explored. At high LET, the 2-finger designs showed the best performances. However, for LET lower than 10 \(\mbox{MeV.cm}^2/\mbox{mg}\), the hardening efficiency of the folded designs is expected to increase as the number of fingers is increased. Increasing the number of fingers increases greatly the final layout area. Thus, a layout technique was proposed to overcome the area overhead of multiple-finger designs. In the diffusion splitting approach, the active diffusion is split into two strips and placed vertically aligned within each other. Besides reducing the layout area, diffusion splitting may also improve the SET cross section depending on the circuit topology, input signal, and ion LET. Due to the strong input dependence of these techniques, it was also proposed to adopt asymmetric designs, i.e., applying the hardening techniques only in the PMOS or NMOS devices, depending on the worst-case input scenario of the logic gate. Voltage variability was also explored due to its impact on the reliability of deeply scaled technologies. The folded designs have shown a higher sensitivity to voltage fluctuation. However, the usage of asymmetric designs showed to reduce it. And, lastly, the in-orbit SET rates were predicted for the LEO and ISS orbits. When the SET rate is only calculated for heavy ions, all the folded designs provided lower rate than the unfolded designs. However, the protons dominate the SEE rates in the LEO and ISS orbits. When protons are taken into account, the 2-finger designs (symmetric and asymmetric) and the asymmetric 4-finger design with DS are the most hardened circuits. Overall, the chapter provides insights into the impact of layout-level RHBD techniques on radiation robustness and explores the potential trade-offs and considerations for their practical implementation.
Highlights
Physical layout design has a significant impact on the fundamental Single-Event Effects (SEE) mechanisms in VLSI circuits, thereby providing an opportunity to enhance radiation robustness through design-based hardening techniques at the layout level.
Gate sizing and transistor stacking were analyzed as RHBD techniques, with both techniques reducing the overall SET cross section and improving reliability, although the efficiency of transistor stacking is highly dependent on the input signal.
The evaluation of transistor folding layouts revealed their potential in enhancing SET immunity by achieving lower SET cross sections and higher threshold Linear Energy Transfer (LET) compared to unfolded designs. The number of fingers utilized in the layout design plays a significant role in the hardening efficiency, with 2-finger designs performing well at high LET values.
Diffusion splitting was proposed as a technique to reduce layout area in multiple-finger designs, with potential SET cross-section improvements depending on circuit topology, input signal, and ion LET.
Asymmetric designs, applying hardening techniques to specific types of devices, can enhance the efficiency of certain hardening techniques.
When evaluating the efficiency of hardening techniques, it is essential to consider variability factors, such as voltage fluctuations and process variations, to ensure robustness in real-world scenarios.
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