Analysis of RSNM and WSNM of 6T SRAM Cell Using Ultra Thin Body FD-SOI MOSFET

The read and write stability of SRAM cell depends on the high-performance CMOS technologies (FD-SOI technology), due to low power dissipation, and high switching and inter-die variability. This paper first analyzed the electrical behavior of ultrathin body fully depleted silicon-on-insulator (UTB FD-SOI) MOSFET. It is demonstrated that the FD-SOI MOSFET has high I_on to I_off ratio (better switching) and low threshold voltage. By taking into account of high switching of UTB FD-SOI MOSFET, it is further used to form a 6T SRAM cell. The read and write behavior of 6T SRAM cell has been studied using the read static noise margin (RSNM) and write static noise margin (WSNM). It is observed that the results obtained from the behavior of SNM show that the design of SRAM cell is more robust and highly stable. Further, the results were compared and contrasted with the reported literature, i.e., FinFET- and SOI MOSFET-based SRAM cell. The structures were designed and simulated using Synopsys TCAD device simulator.