Skip to main content
Top
Published in: Microsystem Technologies 1/2018

20-12-2016 | Technical Paper

Area-efficient and highly accurate antilogarithmic converters with multiple regions of constant compensation schemes

Authors: Chao-Tsung Kuo, Tso-Bing Juang

Published in: Microsystem Technologies | Issue 1/2018

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

In this paper, area-efficient and highly-accurate antilogarithmic converters are proposed. By adopting efficient constant compensation schemes, the proposed antilogarithmic converters could achieve area-efficient with reduced percent errors and reduced delay. Percent errors of the proposed converters could achieve 1.83%, 1.34% and 0.61% for 11-region, 14-region and 28-region constant compensation antilogarithmic conversion, respectively. The complexity of the schemes is very simple since the converters are consisting of only adders/subtractors without shifters compared with previously proposed methods, leading to easy VLSI circuit implementations. It can be used for digital signal processing and digital camera applications; that can simplify greatly the computation efforts.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literature
go back to reference Abed KH, Siferd RE (2003) VLSI implementation of a low-power antilogarithmic converter. IEEE Trans Comput 52(9):1221–1228CrossRef Abed KH, Siferd RE (2003) VLSI implementation of a low-power antilogarithmic converter. IEEE Trans Comput 52(9):1221–1228CrossRef
go back to reference Chaudhary M, Lee P (2014) Two-stage logarithmic converter with reduced memory requirements. IET Comput Digit Tech 8(1):23–29CrossRef Chaudhary M, Lee P (2014) Two-stage logarithmic converter with reduced memory requirements. IET Comput Digit Tech 8(1):23–29CrossRef
go back to reference Combet M, Zonneveld HV, Verbeek L (1965) Computation of the base two logarithm of binary numbers. IEEE Trans Electron Comput 14(6):863–867CrossRef Combet M, Zonneveld HV, Verbeek L (1965) Computation of the base two logarithm of binary numbers. IEEE Trans Electron Comput 14(6):863–867CrossRef
go back to reference Hall EL, Lynch DD, Dwyer SJ (1970) Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans Comput C 19(2):97–105CrossRefMATH Hall EL, Lynch DD, Dwyer SJ (1970) Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans Comput C 19(2):97–105CrossRefMATH
go back to reference Johansson K, Gustafsson O, Wanhammar L (2008) Implementation of elementary functions for logarithmic number systems. IET Comput Digit Tech 2(4):295–304CrossRef Johansson K, Gustafsson O, Wanhammar L (2008) Implementation of elementary functions for logarithmic number systems. IET Comput Digit Tech 2(4):295–304CrossRef
go back to reference Juang TB, Chen SH, Cheng HJ (2009) A lower-error and ROM-free logarithmic converter for digital signal processing applications. IEEE Trans Circuits Syst II Express Briefs 56(12):931–935CrossRef Juang TB, Chen SH, Cheng HJ (2009) A lower-error and ROM-free logarithmic converter for digital signal processing applications. IEEE Trans Circuits Syst II Express Briefs 56(12):931–935CrossRef
go back to reference Juang TB, Meher PK, Jan KS (2011) High-performance logarithmic converters using novel two-region bit-level manipulation schemes. Proceedings of 2011 VLSI-DAT (VLSI Symposium on Design, Automation, and Testing), pp 390–393 Juang TB, Meher PK, Jan KS (2011) High-performance logarithmic converters using novel two-region bit-level manipulation schemes. Proceedings of 2011 VLSI-DAT (VLSI Symposium on Design, Automation, and Testing), pp 390–393
go back to reference Kouretas I, Basetas C, Paliouras V (2013) Low-power logarithmic number system addition/subtraction and their impact on digital filters. IEEE Trans Comput 62(11):2196–2209MathSciNetCrossRefMATH Kouretas I, Basetas C, Paliouras V (2013) Low-power logarithmic number system addition/subtraction and their impact on digital filters. IEEE Trans Comput 62(11):2196–2209MathSciNetCrossRefMATH
go back to reference Liu CW, Ou SH, Chang KC, Lin TC, Chen SK (2016) A low-error, cost-efficient design procedure for evaluating logarithms to be used in a logarithmic arithmetic processor. IEEE Trans Comput 65(4):1158–1164MathSciNetCrossRefMATH Liu CW, Ou SH, Chang KC, Lin TC, Chen SK (2016) A low-error, cost-efficient design procedure for evaluating logarithms to be used in a logarithmic arithmetic processor. IEEE Trans Comput 65(4):1158–1164MathSciNetCrossRefMATH
go back to reference Nam BG, Kim HJ, Yoo HJ (2008) Power and area-efficient unified computation of vector and elementary functions for handheld 3D graphics system. IEEE Trans Comput 57(4):490–504MathSciNetCrossRefMATH Nam BG, Kim HJ, Yoo HJ (2008) Power and area-efficient unified computation of vector and elementary functions for handheld 3D graphics system. IEEE Trans Comput 57(4):490–504MathSciNetCrossRefMATH
go back to reference Paul S, Jayakumar N, Khatri S (2009) A fast hardware approach for approximate, efficient logarithm and antilogarithm computations. IEEE Trans VLSI Syst 17(2):269–277CrossRef Paul S, Jayakumar N, Khatri S (2009) A fast hardware approach for approximate, efficient logarithm and antilogarithm computations. IEEE Trans VLSI Syst 17(2):269–277CrossRef
go back to reference Pineiro JA, Bruguera JD (2004) Algorithm and architecture for logarithm, exponential, and powering computation. IEEE Trans Comput 53(9):1085–1096CrossRef Pineiro JA, Bruguera JD (2004) Algorithm and architecture for logarithm, exponential, and powering computation. IEEE Trans Comput 53(9):1085–1096CrossRef
go back to reference Pineiro JA, Ercegovac MD, Bruguera JD (2005) High-radix logarithm with selection by rounding: algorithm and implementation. J VLSI Sig Proc 40(1):109–123CrossRef Pineiro JA, Ercegovac MD, Bruguera JD (2005) High-radix logarithm with selection by rounding: algorithm and implementation. J VLSI Sig Proc 40(1):109–123CrossRef
go back to reference Stine JE, Schulte MJ (1999) The symmetric table addition method for accurate function approximation. J VLSI Sig Proc 21(2):167–177CrossRef Stine JE, Schulte MJ (1999) The symmetric table addition method for accurate function approximation. J VLSI Sig Proc 21(2):167–177CrossRef
Metadata
Title
Area-efficient and highly accurate antilogarithmic converters with multiple regions of constant compensation schemes
Authors
Chao-Tsung Kuo
Tso-Bing Juang
Publication date
20-12-2016
Publisher
Springer Berlin Heidelberg
Published in
Microsystem Technologies / Issue 1/2018
Print ISSN: 0946-7076
Electronic ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-016-3238-z

Other articles of this Issue 1/2018

Microsystem Technologies 1/2018 Go to the issue