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Published in:
2016 | OriginalPaper | Chapter
15. Asynchronous Assertions!!!
Author : Ashok B. Mehta
Published in: SystemVerilog Assertions and Functional Coverage
Publisher: Springer International Publishing
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Abstract
This chapter is solely devoted to Asynchronous Assertions, meaning the sampling edge of the assertion is not a synchronous clock rather an asynchronous edge. Special focus is on pitfalls of using an asynchronous assertion both as the sampling edge as well as an antecedent expression variable.