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Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators

  • 2023
  • OriginalPaper
  • Chapter
Published in:
Authors
Lorenzo Canese
Gian Carlo Cardarilli
Luca Di Nunzio
Rocco Fazzolari
Marco Re
Sergio Spanó
Published in
Applications in Electronics Pervading Industry, Environment and Society
Publisher
Springer Nature Switzerland

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Abstract

The chapter introduces an automatic IP core generator for FPGA-based Q-Learning hardware accelerators, leveraging the state-of-the-art architecture from Spanó et al. The software, built on MATLAB-Simulink and 'HDL coder' from Mathworks, generates VHDL code compatible with AMD-Xilinx FPGAs. The tool allows customization of Q-Matrix size and parameter bit-depth, offering a seamless transition from software to hardware implementation. Future developments include support for Intel FPGAs and ASICs, as well as the integration of a Policy Generator.
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Title
Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators
Authors
Lorenzo Canese
Gian Carlo Cardarilli
Luca Di Nunzio
Rocco Fazzolari
Marco Re
Sergio Spanó
Copyright Year
2023
Book
Applications in Electronics Pervading Industry, Environment and Society

Print ISBN: 978-3-031-30332-6

Electronic ISBN: 978-3-031-30333-3

Copyright Year: 2023

DOI
https://doi.org/10.1007/978-3-031-30333-3_32
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