Brain-Machine Interface

Continuous monitoring of physiological parameters (e.g., the monitoring of stress and emotion, personal psychological analysis) enabled by brain–machine interface (BMI) circuits is not only beneficial for chronic diseases, but for detection of the onset of a medical condition and the preventive or therapeutic measures. It is expected that the combination of ultra-low power sensor- and ultra-low power wireless communication technology will enable new biomedical devices that will be able to enhance our sensing ability, and can also provide prosthetic functions (e.g., cochlear implants, artificial retina, motor functions). Practical multichannel BMI systems are combined with CMOS electronics for long term and reliable recording and conditioning of intra-cortical neural signals, on-chip processing of the recorded neural data, and stimulating the nervous system in a closed-loop framework. To evade the risk of infection, these systems are implanted under the skin, while the recorded neural signals and the power required for the implant operation is transmitted wirelessly. This migration, to allow proximity between electrodes and circuitry and the increasing density in multichannel electrode arrays, is, however, creating significant design challenges in respect to circuit miniaturization and power dissipation reduction of the recording system. Furthermore, the space to host the system is restricted to ensure minimal tissue damage and tissue displacement during implantation. In this book, this design problem is addressed at various abstraction levels, i.e., circuit level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques. Technology scaling, circuit topologies, architecture trends, (post-silicon) circuit optimization algorithms and yield-constrained, power-per-area minimization framework specifically target power-performance trade-off, from the spatial resolution (i.e., number of channels), feasible wireless data bandwidth and information quality to the delivered power of implantable batteries.

The increasing density and the miniaturization of the functional blocks in these multi-electrode arrays presents significant circuit design challenge in terms of area, power, and the scalability, reliability and expandability of the recording system. In this chapter, we present a neural signal conditioning circuit for biomedical implantable devices, which includes low-noise signal amplification and band-pass filtering. The circuit is realized in a 65 nm CMOS technology, and consumes less than 1.5 μW. The fully differential low-noise amplifier achieves 40 dB closed loop gain, occupies an area of 0.04 mm², and has input referred noise of 3.1 μV_rms over the operating bandwidth 0.1–20 kHz. The capacitive-attenuation band-pass filter with first-order slopes achieves 65 dB dynamic range, 210 mV_rms at 2 % THD and 140 μV_rms total integrated output noise.

Integrated neural implant interface with the brain using biocompatible electrodes provides high yield cell recordings, large channel counts, and access to spike data and/or field potentials with high signal-to-noise ratio. By increasing the number of recording electrodes, spatially broad analysis can be performed that can provide insights into how and why neuronal ensembles synchronize their activity. In this chapter, we present several A/D converter realizations in voltage-, current- and time-domain, respectively, suitable for multichannel neural signal-processing. The voltage-domain SAR A/D converter combines the functionalities of programmable-gain stage and analog to digital conversion, occupies an area of 0.028 mm², and consumes 1.1 μW of power at 100 kS/s sampling rate. The current-mode successive approximation A/D converter is realized in a 65 nm CMOS technology, and consumes less than 367 nW at 40 kS/s, corresponding to a figure of merit of 14 fJ/conversion-step, while operating from a 1 V supply. A time-based, programmable-gain A/D converter allows for an easily scalable, and power-efficient, implantable, biomedical recording system. The time-domain converter circuit is realized in a 90 nm CMOS technology, operates at 640 kS/s, occupies an area of 0.022 mm², and consumes less than 2.7 μW corresponding to a figure of merit of 6.2 fJ/conversion-step.

Robust, power- and area-efficient spike classifier, capable of accurate identification of the neural spikes even for low SNR, is a prerequisite for the real-time, implantable, closed-loop, brain–machine interface. In this chapter, we propose an easily scalable, 128-channel, programmable, neural spike classifier based on nonlinear energy operator spike detection, and a boosted cascade, multiclass kernel support vector machine classification. For efficient algorithm execution, we transform a multiclass problem with the Kesler’s construction and extend iterative greedy optimization reduced set vectors approach with a cascaded method. Since obtained classification function is highly parallelizable, the problem is subdivided and parallel units are instantiated for the processing of each subproblem via energy-scalable kernels. After partition of the data into disjoint subsets, we optimize the data separately with multiple SVMs. We construct cascades of such (partial) approximations and use them to obtain the modified objective function, which offers high accuracy, has small kernel matrices and low computational complexity. The power-efficient classification is obtained with a combination of the algorithm and circuit techniques. The classifier implemented in a 65 nm CMOS technology consumes less than 41 μW of power, and occupies an area of 2.64 mm².

To develop neural prostheses capable of interfacing with neuron cells and neural networks, multichannel probes and the electrodes need to be customized to the anatomy and morphology of the recording site. The increasing density and the miniaturization of the functional blocks in these multielectrode arrays, however, presents significant circuit design challenge in terms of area, power, and the scalability, reliability and expandability of the recording system. In this chapter, we propose a novel method for power per area (PPA) optimization under yield constrains in multichannel neural recording interface. Using a sequence of minimizations with iteratively generated low-dimensional subspaces, our approach renders consistently improved PPA ratio and imposes no restrictions on the distribution of process parameters or how the data enters the constraints. The proposed method can be used with any variability model and subsequently any correlation model, and is not restricted by any particular performance constraint. The experimental results, obtained on the multichannel neural recording interface circuits implemented in CMOS 90 nm technology, demonstrate power savings of up to 26 % and area of up to 22 % without yield penalty.

The healthcare or health-assisting devices, as well as medical care enabled by these devices will enable a level of unprecedented care during each person’s life. Continuous monitoring of physiological parameters (e.g., the monitoring of stress and emotion, personal psychological analysis) enabled by brain–machine interface circuits is not only beneficial for chronic diseases, but for detection of the onset of a medical condition and the preventive or therapeutic measures. Long-term data collection also assists a more exact diagnosis. For non-chronic illnesses, it can assist rehabilitation of patients. It is expected that this new biomedical devices will be able to enhance our sensing ability, and can also provide prosthetic functions (e.g., cochlear implants, artificial retina, motor functions). In this book, this problem is addressed at various abstraction levels, i.e., circuit level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques.