BSIM3 model parameter extraction and performance analysis of a strained p-MOSFET for digital applications

Strain is one of the conventional methods used to enhance the mobility of carriers in metal–oxide–semiconductor field-effect transistors (MOSFETs). The strain is generated due to the lattice mismatch between the thin Si layer and underlying SiGe layers and reduces the effective mass of holes and inter-subband scattering. A compact model for such devices is essential to promote the design of very large-scale integration (VLSI) circuits using strained p-MOSFETs. In this paper, for the first time we propose to use the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method. The extracted model parameters are validated by comparing the results with technology computer-aided design (TCAD) simulations and a simple analytical model. The average error in the direct-current (DC) and alternating-current (AC) characteristics of the model is estimated to be below 1.5%. Finally, the extracted model is used to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random-access memory (SRAM) cells, based on the strained p-MOSFET as a key circuit component. The simulation results show significant performance improvements of the gates in terms of the area, propagation delay, dynamic power consumption, static noise margin, and functional symmetry. By using strained p-MOSFETs in the SRAM cell, the active area of transistors can be reduced by up to 28.8% while at the same the time static power consumption is reduced by 4.8%, the static noise margin is increased by 10.5%, and the write access time is reduced by about 15.6%. These results not only suggest that the strained Si p-MOSFET can improve the performance of VLSI circuits but also confirm that the BSIM3 model with an appropriate parameter extraction method can be used for the design of digital circuits using strained p-MOSFETs.