3. Building a Dynamically Reconfigurable System Through a High-Level Development Flow

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities such as the reduction of the total area required in a FPGA, by means of functioning overlapping, or the modification of the design after its deployment, without the need of configuring completely the system and, therefore, stop its operation. However, the design of partial reconfigurable systems is still a complex task. This work focuses on facilitating the design process of dynamic partially reconfigurable systems and proposes a new development framework using high-level UML/MARTE models. Simulation and VHDL implementation code are generated from these close-to-solution-domain models, according to the specification requirements of the reconfigurable hardware captured in the specifications. To demonstrate this approach, an edge detection-based use case has been implemented with the developed framework showing an efficient outcome and achieving an accurate estimation of resources and expected performance.