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Published in:
2011 | OriginalPaper | Chapter
Chip Planning
Authors : Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Published in: VLSI Physical Design: From Graph Partitioning to Timing Closure
Publisher: Springer Netherlands
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Chip planning
deals with large modules such as caches, embedded memories, and intellectual property (IP) cores that have known areas, fixed or changeable shapes, and possibly fixed locations. When modules are not clearly specified, chip planning relies on
netlist partitioning
(Chap. 2) to identify such modules in large designs. Assigning shapes and locations to circuit modules during chip planning produces
blocks
, and enables early estimates of interconnect length, circuit delay and chip performance. Such early analysis can identify modules that need improvement. Chip planning consists of three major stages (1)
floorplanning
, (2)
pin assignment
, and (3)
power planning
.