Circuits, Systems, and Signal Processing

Guest Editorial: Low Power Computing: Devices, Circuits & Systems for Signal Processing

Basant Kumar Mohanty, Alak Majumdar, Durgesh Nandan, Gyungsu Byun

Enhancing Image Security Using Pseudo-Memristive-Based Steganography

Shikha Khurana, Vandana Khanna, Shaveta Arora, Neeraj Kumar Shukla, Mainak Basu

Optimized Reversible Full Adder Using Lithium Niobate MZI Based Peres Gate

Barnali Chowdhury, Shashank Awasthi, Sanjeev Kumar Metya

ASIC Design of Analog Weighted Mean Filter Frontend for Image Processing Application

K. N. Vijeyakumar, D. Silambarasan, Talluri Vineel Jessy, N. Saravanakumar, M. Manjubala

Truly Mixed-Mode Universal Filter Capable of Operation in MISO and SIMO Configurations with Quadrature Oscillator as an Application

Mohammad Faseehuddin, P. Sivagami, Sadia Shireen, Worapong Tangsrirat

Assessing Cascaded Op-Amp and Pre-Current Amplifier Configurations in Transimpedance Amplifier Interfacing Circuits for Nano-Scale Current-Based Sensor Applications

Mohamed Mamdouh, Sameh O. Abdellatif

Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen

Single Transistor Leakage Control for Low Power CMOS Circuits in Bio-implantable RF Receivers

Shubhankar Majumdar

An Improved Structure for Reducing Bias Current and Offset Voltage of Operational Amplifier

Zhang Zhili, Yao Siyuan, Liu Puyang, Li Cheng, You Lu, Wei Hailong

Energy Efficient Single Phase Adiabatic Logic and Its Application in Ripple Carry Adder Design

Jitendra Kanungo, Jitendra Raghuwanshi, Deepak Sharma, Sudeb Dasgupta

A Power and Area Efficient Analog Classifier for Electrical Impedance Tomography Applications

• Open Access

Vassilis Alimisis, Vasileios Moustakas, Konstantinos Cheliotis, Christos Dimas, Paul P. Sotiriadis

An 0.1 mm2/Ch 40 nm-CMOS 32-Channel Analog Front-End Acquisition Circuit with Analog-Domain Real-Time Offset Reduction and SS-ADC for LFP Neural Signal Recording

Xiaokun Lin, Bin Wang, Lu Liu, Xingchen Zhou, Weitao Yang, Hong Wang

Design and Large Signal Analysis of a 90 nm Novel CMOS Operational Trans-Resistance Amplifier

Amit Gupta, Ashish Raman

Voltage Conveyor Transconductance Amplifier (VCTA): A Novel Analog Building Block for Advanced Analog Signal Processing Applications

Chandan Kumar Choubey, Manoj Kumar Tiwari, Aruna Pathak, Durgesh Nandan

Work Function Tuning in Strain Induced Double Gated Junctionless Transistor: A Device to Circuit Performance Study for Sub-20nm Nodes

Tika Ram Pokhrel, Alaaddin Al-Shidaifat, Hanjung Song, Alak Majumder

Novel Charge Plasma Vertically Stacked Dopingless Nanosheet Field-Effect Transistor (DL-NSFET): Proposal and Extensive Analysis

Abhishek Chauhan, Ashish Raman

Optimized Fredkin Gate and its Application to Design an Ancilla-Delay-Cost Efficient () Reversible RAM

Barnali Chowdhury, Shashank Awasthi, Sanjeev Kumar Metya

Dynamic Header Switch to Influence Switching Current Profile of an IC Chip

Vijay Pratap Yadav, Vipin Kumar Singh, Ashish Ranjan Kumar, Tika Ram Pokhrel, Sanjeev Kumar Metya, Alak Majumder

FiSA: Efficient Fixed-Point Stream Architecture for FastICA Implementing on FPGA

Lianyou Lai, Yazhe Zhang, Ling Qin, Weijian Xu

Available Residual Capacity Prediction Model for the Life Cycle of Storage Battery Considering Multiple Disturbances

Rongkun Wang, Dong Wang, Wenjie Huang, Liming Song

Miniaturization of Insertable Cardiac Monitor: ECG Signal Processing Based on Stochastic Computing

Zhihao Chen, Tian Ban

Single-Channel Communication Signal Source Estimation Algorithm Based on Diagonal Loading

Keshan Deng, Jianqiong Zhang, Jiefeng Zang

A Novel Ensemble Empirical Decomposition and Time–Frequency Analysis Approach for Vibroarthrographic Signal Processing

• Open Access

Surbhi Bhatia Khan, A. Balajee, S. Sheik Mohideen Shah, T. R. Mahesh, Mohammad Alojail, Indrajeet Gupta

An Approach of ISI Elimination and High-Speed Data Reconstruction in Lossy On-Chip Serial Link

Anirban Tarafdar, Alak Majumder, Biman Debbarma, Bidyut K. Bhattacharyya

Efficient Edge-AI with Binarized Neural Networks and CMOS Image Sensors: A Sparsity-Driven Approach

Wilfred Kisku, Amandeep Kaur, Deepak Mishra

A Performance-Centric Topology for Hybrid Wireless-Network-on-Chip

Munshi Mostafijur Rahaman, Prasun Ghosal, Chandan Giri

Design and Analysis of a High-Speed Approximate Restoring Array Based Log Divider (ARLD)

P. Gowtham, A. Anita Angeline, P. Sasipriya

Performance Analysis of Low Power Inexact Recursive Multipliers for Image Processing Applications

S. Harichandra Prasad, K. Kumar

Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET

Kattekola Naresh, Y. Padma Sai, Ch. Ganesh, Shubhankar Majumdar

Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition

Sudhanshu Janwadkar, Rasika Dhavse