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Journal of Electronic Testing
Published in:

30-09-2021

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits

Authors: Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, James Chien-Mo, Tsung-Te Liu, I-Wei Chiu

Published in: Journal of Electronic Testing | Issue 4/2021

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Abstract

It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip.
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Metadata
Title
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits
Authors
Tsai-Chieh Chen
Chia-Cheng Pai
Yi-Zhan Hsieh
Hsiao-Yin Tseng
James Chien-Mo
Tsung-Te Liu
I-Wei Chiu
Publication date
30-09-2021
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 4/2021
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-021-05963-z

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