CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications

This paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high Static Noise Margins (STM) of 100–120 mV. The hysteresis in the STM curve of the CNFET Schmitt SRAM has been achieved through proper adjustment of the threshold voltage \(V_{th}\) of the different CNFETs used to implement the SRAM. The \(V_{th}\) of the CNFET can be set to the required level by selecting the appropriate chiral vectors of the CNFET. The CNFET based SRAM consumes merely 3.2 pW of power as compared to 19.5 pW of power required by the same SRAM implemented with MOSFET devices. The CNFET SRAM also has an average propagation delay of 31 ps, which is significantly lower than the delay of 250 ns experienced in CMOS-based SRAM. A simplified multi-\(V_{th}\) 6T CNFET SRAM design is also proposed, which consumes merely 0.1 pW of power, thus enabling a 99% reduction in total power consumption in contrast to the conventional CMOS SRAM design. The device characteristics of the CNFET has been benchmarked with 45 nm CMOS devices. The improvement in the performance of the CNFET based SRAMs can be attributed to the 10 times higher \(I_{ON}\):\(I_{OFF}\) ratio and 18 times higher \(I_{ON}\):\(C_{GG}\) ratio of the CNFET as compared to the MOSFETs.