Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
DE
EN
Books
Journals
Events
Topic Page
Marketing
Log in
Learn more about individual access
Request company access
12th International Engine Congress 2025 | 25. + 26. February 2025

Meeting Place for the Powertrain and Sustainable Fuels Community

The congress will examine the future role of the internal combustion engine and its non-fossil fuels from a global perspective with leading experts. Be part of it! More information and booking options are available on our website.
EXTENDED SEARCH
Log in
Top
Journal of Computational Electronics
Published in:

24-07-2023

Compact drain current model of a double-gate raised buried oxide TFET for integrated circuit application

Authors: Sirisha Meriga, Brinda Bhowmick

Published in: Journal of Computational Electronics | Issue 5/2023

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

A compact model for the drain current of a double-gate tunnel field-effect transistor (TFET) operating in the subthreshold and super-threshold regions is proposed in this paper. Using this drain current model, the key parameter for integrated analog circuit design technology, namely the transconductance-to-drain current ratio, was extracted. As this method is simple, it can be readily implemented for any type of dual-gate TFET with a few fitted parameters. The drain current calculated using this model was compared with the simulated drain current using 2D Sentaurus TCAD software, which validated the performance of the TFET. The proposed method can be adapted to obtain the desired transconductance to operate TFETs in the gigahertz range with very low-milliwatt power consumption.
previous article Low-frequency noise performance of a molybdenum ditelluride double-gate MOSFET
next article Finite-element simulation of interfacial resistive switching by Schottky barrier height modulation

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
Literature
1.
Crupi, G., Schreurs, D.M., Raskin, J.P., Caddemi, A.: A comprehensive review on microwave FinFET modelling for progressing beyond the state of art. Solid-State Electron. 80, 81–95 (2013)CrossRef
2.
Anvarifard, M.K., Orouji, A.A.: Enhanced critical electrical characteristics in a nanoscale low-voltage SOI MOSFET with dual tunnel diode. IEEE Trans. Electron Devices 62(5), 1672–1676 (2015)CrossRef
3.
Anvarifard, M.K., Orouji, A.A.: Stopping electric field extension in a modified nanostructure based on SOI technology-a comprehensive numerical study. Superlattices Microstruct. 111, 206–220 (2017)CrossRef
4.
Hu, C., Patel, P., Bowonder, A., Jeon, K., Kim, S.H., Loh, W.Y., Kang, C.Y., Oh, J., Majhi, P., Javey, A., Liu, T.J.: Prospect of tunneling green transistor for 0.1V CMOS. In: International Electron Devices Meeting. IEEE, pp. 1–16 (2010)
5.
Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)CrossRef
6.
Bangsaruntip, S., Cohen, G.M., Majumdar, A., Sleight, J.W.: Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Electron Device Lett. 31(9), 903–905 (2010)CrossRef
7.
Kim, S.W., Kim, J.H., Liu, T.-J.K., Choi, W.Y., Park, B.-G.: Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans. Electron Devices 63, 1774–1778 (2016)CrossRef
8.
Krishna Mohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double-gate strained-Ge heterostructure tunneling fet (TFET) with record high drive currents and ≪ 60mV/dec subthreshold slope. In: IEEE International Electron Devices Meeting, pp. 1–3 (2008)
9.
Kim, M., Wakabayashi, Y.K., Nakane, R., Yokoyama, M., Takenaka, M., Takagi, S.: High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs–impact of channel strain, MOS interfaces and back gate on the electrical properties. IEICE Tech. Rep. 114(421), 9–12 (2015)
10.
Kim, S.W., Choi, W.Y.: Hump effects of germanium/silicon heterojunction tunnel field-effect transistors. IEEE Trans. Electron Devices 63(6), 2583–2588 (2016)CrossRef
11.
Ohno, T., Kado, Y., Harada, M., Tsuchiya, T.: Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique. IEEE Trans. Electron Devices 42(8), 1481–1486 (1995)CrossRef
12.
Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57(4), 827–834 (2010)CrossRef
13.
Boucart, K., Ionescu, A.M.: Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric. In: European solid-state device research conference. IEEE, pp 383–386 (2006)
14.
Dutta, R., Paitya, N.: TCAD performance analysis of PIN tunneling FETS under surrounded gate structure. In: 2nd international conference on advances in science & technology (ICAST) (2019)
15.
Dutta, R., Konar, S.C., Paitya, N.: Influence of gate and channel engineering on multigate tunnel FETs: a review. In: Computational Advancement in Communication Circuits and Systems: Proceedings of ICCACCS 2018, pp. 345–355 (2020)
16.
Seabaugh, A.C., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010)CrossRef
17.
Mallik, A., Chattopadhyay, A.: Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications. IEEE Trans. Electron Devices 59(4), 888–894 (2012)CrossRef
18.
Vittoz, E., Fellrath, J.: CMOS analog integrated circuits based on weak inversion operations. IEEE J. Solid-State Circuits 12(3), 224–231 (1977)CrossRef
19.
Silveira, F., Flandre, D., Jespers, P.G.: A g/sub m//I/sub D/based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE J. Solid-State Circuits 31(9), 1314–1319 (1996)CrossRef
20.
Trivedi, A.R., Carlo, S., Mukhopadhyay, S.: Exploring tunnel-FET for ultralow power analog applications: a case study on operational transconductance amplifier. In: ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, pp. 1–6 (2013)
21.
Banerjee, S., Richardson, W., Coleman, J., Chatterjee, A.: A new three-terminal tunnel device. IEEE Electron Device Lett. 8(8), 347–349 (1987)CrossRef
22.
Vandenberghe, W.G., Verhulst, A.S., Groeseneken, G., Sorée, B., Magnus, W.: Analytical model for a tunnel field-effect transistor. In: Proceedings of the Mediterranean Electrotechnical Conference - MELECON, pp. 923–928 (2008)
23.
Mookerjea, S., Krishnan, R., Datta, S., Narayanan, V.: Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation. IEEE Trans. Electron Devices 56(9), 2092–2098 (2009)CrossRef
24.
Mookerjea, S., Krishnan, R., Datta, S., Narayanan, V.: On enhanced miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 30(10), 1102–1104 (2009)CrossRef
25.
Bardon, M.G., Neves, H.P., Peurs, R., Hoof, C.V.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57(4), 827–834 (2010)CrossRef
26.
Syamal, B., Bose, C., Sarkar, C.K., Mohankumar, N.: Effect of single HALO doped channel in tunnel junction: a 2-D modeling study. In: IEEE International Conference on EDSSC, pp. 1–4 (2010)
27.
Bhowmick, B., Baishya, S.: A physics based model for electrical parameters of double gate hetero-material nano scale tunnel FET. Int. J. Appl. Inf. Syst. 1(3), 25–32 (2012)
28.
Graef, M., Holtij, T., Hain, F., Kloes, A., Iniguez, B.: Two-dimensional physics-based modeling of electrostatics and band-to-band tunneling in tunnel-FETs. Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, pp. 81–85 (2013)
29.
Kumar, S., Goel, E., Singh, K., Singh, B., Kumar, M., Jit, S.: A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high-k stacked gate-oxide structure. IEEE Trans. Electron Devices 63(8), 3291–3299 (2016)CrossRef
30.
Goswami, R., Bhowmick, B.: An analytical model of drain current in a nanoscale circular gate TFET. IEEE Trans. Electron Devices 64(1), 45–51 (2017)CrossRef
31.
Dutta, R., Sarkar, S.K.: Analytical modeling and simulation-based optimization of broken gate TFET structure for low power applications. IEEE Trans. Electron Devices 66(8), 3513–3520 (2019)CrossRef
32.
Kaur, S., Raman, A., Sarin, R.K.: An explicit surface potential, capacitance and drain current model for double-gate TFET. Superlattices Microstruct. 140, 106431 (2020)CrossRef
33.
Dutta, R., Subash, T., Paitya, N.: Improved DC performance analysis of a novel asymmetric extended source tunnel FET for fast switching application (2021)
34.
Dutta, R., Subash, T.D., Paitya, N.: Improved DC performance analysis of a novel asymmetric extended source tunnel FET (AES-TFET) for fast switching application. SILICON 14(8), 3835–3841 (2022)CrossRef
35.
Lu, H., Kim, J.W., Esseni, D., Seabaugh, A.: Continuous semiempirical model for the current-voltage characteristics of tunnel FETs. In: 15th International Conference on Ultimate Integration on Silicon (ULIS). IEEE, pp. 25–28 (2014)
36.
Lu, H., Esseni, D., Seabaugh, A.: Universal analytic model for tunnel FET circuit simulation. Solid-State Electron. 108, 110–117 (2015)CrossRef
37.
Barboni, L., Siniscalchi, M., Sensale-Rodriguez, B.: TFET-based circuit design using the transconductance generation efficiency ${g}{m}/{I}{d} method. IEEE J. Electron Devices Soc. 3(3), 208–216 (2015)CrossRef
38.
Khairnar, A.G., et al.: Electrical properties of HfO2 high-k thin-film MOS capacitors for advanced CMOS technology. Indian J. Phys. 89, 1177–1181 (2015)CrossRef
39.
Alam, F., et al.: All-water-driven high-k HfO2 gate dielectrics and applications in thin film transistors. Nanomaterials 13(4), 694 (2023)CrossRef
40.
Sirisha, M., Bhowmick, B.: Investigation of a dual gate pocket-doped drain engineered tunnel FET and its reliability issues. Appl. Phys. A 129(2), 104 (2023)CrossRef
41.
Khakifirooz, A., Nayfeh, O.M., Antoniadis, D.: A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters. IEEE Trans. Electron Devices 56(8), 1674–1680 (2009)CrossRef
42.
Wright, G.T.: Threshold modelling of MOSFETs for CAD of CMOS-VLSI. Electron. Lett. 6(21), 223–224 (1985)CrossRef
43.
Boucart, K., Ionescu, A.M.: A new definition of threshold voltage in tunnel FETs. Solid-State Electron. 52(9), 1318–1323 (2008)CrossRef
44.
Yu, Y.S., Najam, F.: Compact current model of single-gate/double-gate tunneling field-effect transistors. J. Electr. Eng. Technol. 12(5), 2014–2020 (2017)
45.
Sentaurus Device User Guide, Synopsys, Inc. (2011)
Metadata
Title
Compact drain current model of a double-gate raised buried oxide TFET for integrated circuit application
Authors
Sirisha Meriga
Brinda Bhowmick
Publication date
24-07-2023
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 5/2023
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-023-02077-x

Other articles of this Issue 5/2023

Special issue on ab initio simulations of electron and phonon transport in nanostructures

A deterministic Wigner transport equation solver with infinite correlation length

Monte Carlo study of carrier transport in two-dimensional transition metal dichalcogenides: high-field characteristics and MOSFET simulation

Design considerations for engineering negative capacitance FET through multilayered channel and / double-gate stacks: an ab initio and NEGF study

Electronic transport computation in thermoelectric materials: from ab initio scattering rates to nanostructures

  • Open Access

Deep-learning-based neural network for design of a dual-band coupled-line trans-directional coupler