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Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique

  • 2021
  • OriginalPaper
  • Chapter
Published in:
Authors
Deepika Sharma
Shilpi Birla
Published in
Micro-Electronics and Telecommunication Engineering
Publisher
Springer Singapore

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Abstract

The chapter delves into the comparative study of CMOS and FinFET-based SRAM cells, focusing on low power design using the Self-controllable Voltage Leveling (SVL) technique. It begins by highlighting the key design challenges in optimizing power for battery-operated devices and portable electronics. The study introduces an improved 10T SRAM cell in 32nm CMOS and FinFET technology, capable of performing read/write operations. The research method includes the sleep transistor technique and drowsy cache technique, but the SVL technique is shown to be the most effective in reducing static power dissipation. The results and analysis demonstrate that the proposed FinFET design cell offers improvements in Hold Stability Noise Margin (HSNM) and Read Stability Noise Margin (RSNM) compared to CMOS. The chapter concludes by emphasizing the potential of the SVL technique in designing SRAM cells for ultra-low power applications, providing a significant reduction in static power dissipation.
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previous chapter A Review on MIMO Dielectric Resonator Antenna for 5G Application
next chapter Capacity Evaluation and Analysis of Long Range for IoT
Title
Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique
Authors
Deepika Sharma
Shilpi Birla
Copyright Year
2021
Publisher
Springer Singapore
Book
Micro-Electronics and Telecommunication Engineering

Print ISBN: 978-981-334-686-4

Electronic ISBN: 978-981-334-687-1

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-33-4687-1_2
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